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| 50 mips 16 kb flash, 512b ee prom mixed-signal mcu c8051f39x/37x preliminary rev. 0.71 8/12 copyright ? 2012 by silicon laboratories c8051f39x/37x this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. analog peripherals (?f390/2/4/6/8 and ?f370/4) - 10-bit adc ? programmable throughput up to 500 ksps ? up to 16 external inputs, programmable as single- ended or differential ? reference from on-chip voltage reference, v dd or external vref pin ? internal or external start of conversion sources - two 10-bit current output dacs ? supports output through resets for continuous operation - comparator ? programmable hysteresis and response time ? configurable as interrupt or reset source - precision temperature sensor ? accurate to 2 c across temperature range with no user calibration on-chip debug - on-chip debug circuitry facilitates full speed, non- intrusive in-system debug (no emulator required) - provides breakpoints, single stepping, inspect/modify memory and registers low power - 160 a/mhz active mode with 49 mhz internal precision oscillator - 200 na stop mode current temperature range - ?40 to +85 c (?f37x) - ?40 to +105 c (?f39x) package - 24-pin qfn (?f390/1/4/5 and ?f37x) - 20-pin qfn (?f392/3/6/7/8/9) high-speed 8051 c core - pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - up to 50 mips throughput with 50 mhz clock - expanded interrupt handler memory - up to 1 kbytes internal data ram (256 + 768) - up to 16 kb flash; in-system programmable in 512- byte sectors - 512 bytes of byte-programmable eeprom; 1 mil- lion write/erase cycles (?f37x) digital peripherals - 21 or 17 port i/o - uart, 2 smbus (i 2 c compatible), and spi serial ports - six general purpose 16-bit counter/timers - 16-bit programmable counter array (pca) with three capture/compare modules and pwm functionality clock sources - 49 mhz 2% precision internal oscillator ? supports crystal-less uart operation ? low-power suspend mode with fast wake time - 80 khz low-frequency, low-power oscillator - external oscillator: crystal, rc, c, or cmos clock - can switch between clock s ources on-the-fly; useful in power saving modes supply voltage 1.8 to 3.6 v - built-in voltage supply monitor analog peripherals 16/8 kb isp flash 1024 b sram por debug circuitry flexible interrupts 8051 cpu (50 mips) digital i/o 49 mhz precision internal oscillator high-speed controller core crossbar wdt port 0 80 khz low frequency internal oscillator port 1 p2.1? p2.4* p2.0 *p2.1?2.4 qfn24 only voltage comparator + ? vref a m u x precision temp sensor 10-bit current dac 10-bit current dac 10-bit 500 ksps adc ?f390/2/4/6/8 & ?f370/4 only uart smbus0 pca0 timer 0 timer 1 timer 2 timer 3 spi timer 4 timer 5 smbus1 pca1 pca2 temp sensor 512 b eeprom www.datasheet.net/ datasheet pdf - http://www..co.kr/
c8051f39x/37x 2 preliminary rev. 0.71 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 3 c8051f39x/37x table of contents 1. system overview ........ ................ ................. ................ ................. ................ ........... 17 2. ordering information ....... ................ ................ ................. .............. .............. ........... 20 3. c8051f33x compatibility ........... ................. ................ ................. ................ ........... 21 3.1. hardware incompatibilities ... ................. ................ ................. ................ ........... 21 4. pin definitions........... ................ ................ ................. ................ ................. ............. 22 5. qfn-20 package specifications ..... ................ ................. .............. .............. ........... 28 6. qfn-24 package specifications ..... ................ ................. .............. .............. ........... 30 7. electrical characteristics ......... ................ ................. ................ ................. ............. 32 7.1. absolute maximum specificat ions................ .............. .............. .............. ........... 32 7.2. electrical characteri stics ................ .............. .............. .............. .............. ........... 33 7.3. typical performance curves ... ................ ................ ................. .............. ........... 44 8. precision temperature sensor (c8051f390/2/4/6/8 and c8051f 370/4 only).............. .............. ............... ........... ......... 45 8.1. temperature in two?s comple ment ............. .............. .............. .............. ........... 45 9. 10-bit adc (adc0, c8051f390/2/4/6/8 and c 8051f370/4 only) ....... ........... ......... 48 9.1. output code formatting ....... ................. ................ ................. ................ ........... 49 9.2. modes of operation ... ................ ................ ................. .............. .............. ........... 50 9.2.1. starting a conversion...... ................ ................ ................. .............. ........... 50 9.2.2. tracking modes............... ................ ................ ................. .............. ........... 51 9.2.3. settling time requirement s................. .............. .............. .............. ........... 52 9.3. programmable window detector ............... ................. .............. .............. ........... 56 9.3.1. window detector example. ............... ................. .............. .............. ........... 58 9.4. adc0 analog multiplexer (c8051f390/ 2/4/6/8 and c8051f370/ 4 only) .......... 59 10. temperature sensor (c8051f 390/2/4/6/8 and c8051f370/4 only).......... ........... 62 10.1. calibration ............ ................. ................ ................ ................. .............. ........... 63 11. 10-bit current mode dacs (ida0, ida1, c8051f390/ 2/4/6/8 and c8051f370/4 only) ....... ............... ........... ......... 64 11.1. idac output scheduling ....... ................ ................ ................. .............. ........... 64 11.1.1. update output on-demand .. ................. .............. ............... ........... ......... 64 11.1.2. update output based on timer overflow ................. ................. ............. 66 11.1.3. update output based on cnvstr edge .. ............... ................. ............. 66 11.2. idac reset behavior ......... ................. ................ ................. ................ ........... 66 11.3. idac output mappin g .................. .............. .............. .............. .............. ........... 66 12. voltage reference options ...... ................. ................ ................. ................ ........... 71 13. voltage regulator ....... ................. ................ ................ ................. .............. ........... 73 13.1. power modes........... ................ ................ ................. .............. .............. ........... 73 14. comparator0.............. ................ ................. ................ ................. ................ ........... 74 14.1. comparator multiplexer ...... ................. ................ ................. ................ ........... 78 15. cip-51 microcontroller.............. ................. ................ ................. ................ ........... 80 15.1. instruction set....... ................. ................ ................ ................. .............. ........... 81 15.1.1. instruction and cpu timing ............... .............. .............. .............. ........... 81 15.2. cip-51 register descriptions .. ................ ................. .............. .............. ........... 85 16. prefetch engine......... ................ ................. ................ ................. ................ ........... 90 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 4 preliminary rev. 0.71 17. memory organization .... ................ ................ ................. .............. .............. ........... 91 17.1. program memory....... ................ ................. .............. .............. .............. ........... 92 17.1.1. movx instruction and program memory .. ................ ................. ............. 92 17.2. data memory ........... ................ ................ ................. .............. .............. ........... 92 17.2.1. internal ram ..... ................ ................. .............. .............. .............. ........... 92 17.2.1.1. general purpose regi sters ................ ................. ................ ........... 93 17.2.1.2. bit addressable locat ions ............. .............. ............... ........... ......... 93 17.2.1.3. stack ........... .............. .............. .............. .............. .............. ........... 93 17.2.2. external ram ..... ............... ................. .............. .............. .............. ........... 93 18. device id registers ... ............... ................. ................ ................. ................ ........... 95 19. special function registers...... ................. ................ ................. ................ ........... 99 19.1. sfr paging ............. ................ ................ ................. .............. .............. ........... 99 19.2. interrupts and automatic sfr paging ................. ................. ................ ........... 99 19.3. sfr page stack exampl e ................ ................. ................ ................. ........... 101 20. interrupts ............ ................ ................. .............. .............. .............. .............. ......... 115 20.1. mcu interrupt sour ces and vectors........... .............. .............. .............. ......... 116 20.1.1. interrupt priorities....... ................. ................ ................. ................ ......... 116 20.1.2. interrupt latency ............. ................ ................. .............. .............. ......... 116 20.2. interrupt register descripti ons .............. ................ ................. .............. ......... 118 20.3. external interrupts int0 and int1........... ................. .............. .............. ......... 126 21. flash memory.............. ................. ................ ................ ................. .............. ......... 129 21.1. programming the flash memo ry ............... .............. .............. .............. ......... 129 21.1.1. flash lock and key functi ons ............... .............. ............... ........... ....... 129 21.1.2. flash erase procedure ..... ................. .............. .............. .............. ......... 129 21.1.3. flash write procedure ..... ............... ................. .............. .............. ......... 130 21.2. non-volatile data storage .. ................. ................ ................. ................ ......... 130 21.3. security options ...... ................ ................ ................. .............. .............. ......... 131 21.4. flash write and erase guidel ines .............. .............. .............. .............. ......... 133 21.4.1. v dd maintenance and the v dd monitor ........... .............. .............. ......... 133 21.4.2. pswe maintenance ............. .............. .............. .............. .............. ......... 133 21.4.3. system clock ...... ................. .............. .............. .............. .............. ......... 134 22. eeprom (c8051f37x) ................. ................ ................ ................. .............. ......... 138 22.1. eeprom communication protoc ol............... .............. ............... ........... ....... 138 22.1.1. slave addres s byte................ .............. .............. .............. .............. ....... 139 22.1.2. acknowledgement (ack) ..... .............. .............. .............. .............. ......... 139 22.1.3. not-acknowledgement (nac k)................. ................ ................. ........... 139 22.1.4. reset.......... ................ ................. ................ ................. ................ ......... 139 22.2. write operation ....... ................ ................ ................. .............. .............. ......... 140 22.3. read operation ....... ................ ................ ................. .............. .............. ......... 141 22.3.1. current address read .... ................ ................. .............. .............. ......... 141 22.3.2. selective address read.. ................ ................. .............. .............. ......... 143 23. cyclic redundancy check unit (crc0).......... .............. .............. .............. ......... 145 23.1. crc algorithm......... ................ ................ ................. .............. .............. ......... 145 23.2. preparing for a crc calculatio n ................ .............. .............. .............. ......... 147 23.3. performing a crc calculation . ............... ................. .............. .............. ......... 147 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 5 c8051f39x/37x 23.4. accessing the crc0 result .... ................ ................. .............. .............. ......... 147 23.5. crc0 bit reverse feature.... ................ ................ ................. .............. ......... 147 24. reset sources ........... ................ ................. ................ ................. ................ ......... 153 24.1. power-on reset ...... ................ ................ ................. .............. .............. ......... 154 24.2. power-fail reset / vdd moni tor .................... .............. ............... ........... ....... 155 24.3. external reset ................ .............. .............. .............. .............. .............. ......... 157 24.4. missing clock detector reset . ................ ................. .............. .............. ......... 157 24.5. comparator0 reset ............ ................. ................ ................. ................ ......... 157 24.6. pca watchdog timer reset ..... ................. .............. .............. .............. ......... 157 24.7. flash error reset .... ................ ................ ................. .............. .............. ......... 157 24.8. software reset ........ ................ ................ ................. .............. .............. ......... 157 25. power management modes...... ................. ................ ................. ................ ......... 159 25.1. idle mode....... ................. .............. .............. .............. .............. .............. ......... 159 25.2. stop mode ............... ................ ................ ................. .............. .............. ......... 160 25.3. suspend mode .......... ................ ................. .............. .............. .............. ......... 160 26. oscillators and clock selection ............ ................. ................ ................. ........... 162 26.1. system clock selection...... ................. ................ ................. ................ ......... 163 26.2. programmable internal high-frequency (h-f) oscillator .. ................. ........... 164 26.2.1. internal oscillator sus pend mode ............... ................. ................ ......... 164 26.3. programmable internal lo w-frequency (l-f) oscillator ... ................. ........... 166 26.3.1. calibrating the internal l-f oscillator........ ................ ................. ........... 166 26.4. internal low-power oscillator........... ................. ................ ................. ........... 167 26.5. external oscillator drive circuit........ ................. ................ ................. ........... 167 26.5.1. external crystal mode................. ................ ................. ................ ......... 167 26.5.2. external rc example...... ................ ................. .............. .............. ......... 169 26.5.3. external capacitor exam ple............... .............. .............. .............. ......... 169 27. port input/output ...... ................ ................. ................ ................. ................ ......... 171 27.1. port i/o modes of operation. ................... ................. .............. .............. ......... 172 27.1.1. port pins configured fo r analog i/o.......... ................ ................. ........... 172 27.1.2. port pins configured fo r digital i/o.......... ................ ................. ........... 172 27.2. assigning port i/ o pins to analog and digital functi ons................. .............. 173 27.2.1. assigning port i/o pins to analog f unctions ............ ................. ........... 173 27.2.2. assigning port i/o pins to digital f unctions............ ............ ........... ....... 174 27.2.3. assigning port i/o pins to external event trig ger functions.. .............. 175 27.3. priority crossbar decoder .. ................. ................ ................. ................ ......... 176 27.4. port i/o initializatio n ................ ................ ................. .............. .............. ......... 178 27.5. port match ............ ................. ................ ................ ................. .............. ......... 181 27.6. special function regist ers for accessing an d configuring port i/o ............. 183 28. smbus0 and smbus1 (i2c compat ible)............ .............. .............. .............. ....... 190 28.1. supporting document s ................. .............. .............. .............. .............. ......... 191 28.2. smbus configuration.......... ................. ................ ................. ................ ......... 191 28.3. smbus operation ...... ................ ................. .............. .............. .............. ......... 191 28.3.1. transmitter vs. receiver .. ............... ................. .............. .............. ......... 192 28.3.2. arbitration........ ................ ................ ................. .............. .............. ......... 192 28.3.3. clock low extensio n................ ................. ................ ................. ........... 192 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 6 preliminary rev. 0.71 28.3.4. scl low timeout... .............. .............. .............. .............. .............. ......... 192 28.3.5. scl high (smbus free) timeout ............... ................. ................ ......... 193 28.4. using the smbus..... ................ ................ ................. .............. .............. ......... 193 28.4.1. smbus configuration regi ster............. .............. .............. .............. ....... 193 28.4.2. smbus pin swap ............ ................ ................. .............. .............. ......... 195 28.4.3. smbus timing control ..... ............... ................. .............. .............. ......... 195 28.4.4. smbncn control register ................. .............. .............. .............. ......... 199 28.4.4.1. software ack generat ion .................. ................. ................ ......... 199 28.4.4.2. hardware ack generat ion ............... ................ ................. ........... 199 28.4.5. hardware slave addre ss recognition ........ ................. ................ ......... 202 28.4.6. data register .... ................ ................. .............. .............. .............. ......... 207 28.5. smbus transfer modes......... ................ ................ ................. .............. ......... 209 28.5.1. write sequence (master) .. ................. .............. .............. .............. ......... 209 28.5.2. read sequence (master) ..... .............. .............. .............. .............. ......... 210 28.5.3. write sequence (slave) ... ............... ................. .............. .............. ......... 211 28.5.4. read sequence (slave) .... ................. .............. .............. .............. ......... 212 28.6. smbus status decodi ng................... ................. ................ ................. ........... 212 29. uart0 ................. ................ ................. .............. .............. .............. .............. ......... 218 29.1. enhanced baud rate generati on............ ................. .............. .............. ......... 219 29.2. operational modes ............. ................. ................ ................. ................ ......... 220 29.2.1. 8-bit uart ........ ................ ................. .............. .............. .............. ......... 220 29.2.2. 9-bit uart ........ ................ ................. .............. .............. .............. ......... 221 29.3. multiprocessor communication s ................ .............. .............. .............. ......... 222 30. enhanced serial peripheral in terface (spi0) ......... ................ ................. ........... 226 30.1. signal descriptions.. ................ ................ ................. .............. .............. ......... 227 30.1.1. master out, slave in (m osi).............. .............. .............. .............. ......... 227 30.1.2. master in, slave out (m iso).............. .............. .............. .............. ......... 227 30.1.3. serial clock (sck ) ................. .............. .............. .............. .............. ....... 227 30.1.4. slave select (nss) ....... ................ ................ ................. .............. ......... 227 30.2. spi0 master mode op eration .............. ................ ................. ................ ......... 228 30.3. spi0 slave m ode operation .................. ................ ................. .............. ......... 229 30.4. spi0 interrupt sources ....... ................. ................ ................. ................ ......... 230 30.5. serial clock phase and polari ty .............. ................. .............. .............. ......... 230 30.6. spi special function register s .................. .............. .............. .............. ......... 232 31. timers ................... ................. ................ ................ ................. ................ .............. 24 0 31.1. timer 0 and timer 1 ... ............... ................. .............. .............. .............. ......... 243 31.1.1. mode 0: 13-bit counter/timer ............ .............. .............. .............. ......... 243 31.1.2. mode 1: 16-bit counter/timer ............ .............. .............. .............. ......... 244 31.1.3. mode 2: 8-bit counter/timer with auto-reload.... ............... ........... ....... 245 31.1.4. mode 3: two 8-bit co unter/timers (timer 0 only)... ........... ........... ....... 246 31.2. timer 2 .......... ................. .............. .............. .............. .............. .............. ......... 251 31.2.1. 16-bit timer with auto-rel oad................ .............. ............... ........... ....... 251 31.2.2. 8-bit timers with auto -reload............ .............. .............. .............. ......... 252 31.2.3. low-frequency oscillator (lfo) captur e mode ................. ........... ....... 253 31.3. timer 3 .......... ................. .............. .............. .............. .............. .............. ......... 257 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 7 c8051f39x/37x 31.3.1. 16-bit timer with auto-rel oad................ .............. ............... ........... ....... 257 31.3.2. 8-bit timers with auto -reload............ .............. .............. .............. ......... 258 31.3.3. low-frequency oscillator (lfo) captur e mode ................. ........... ....... 259 31.4. timer 4 .......... ................. .............. .............. .............. .............. .............. ......... 263 31.4.1. 16-bit timer with auto-rel oad................ .............. ............... ........... ....... 263 31.4.2. 8-bit timers with auto -reload............ .............. .............. .............. ......... 264 31.5. timer 5 .......... ................. .............. .............. .............. .............. .............. ......... 268 31.5.1. 16-bit timer with auto-rel oad................ .............. ............... ........... ....... 268 31.5.2. 8-bit timers with auto -reload............ .............. .............. .............. ......... 269 32. programmable counter array............ .............. .............. .............. .............. ......... 273 32.1. pca counter/timer ............ ................. ................ ................. ................ ......... 274 32.2. pca0 interrupt sources...... ................. ................ ................. ................ ......... 275 32.3. capture/compare modules ..... ................ ................. .............. .............. ......... 276 32.3.1. edge-triggered capture m ode................ .............. ............... ........... ....... 277 32.3.2. software timer (compare) mode................ ................. ................ ......... 278 32.3.3. high-speed output mode ............... ................. .............. .............. ......... 279 32.3.4. frequency output mode ............... ................ ................. .............. ......... 280 32.3.5. 8-bit, 9-bit, 10-bit and 11-bit pulse width modulator modes ................ 280 32.3.5.1. 8-bit pulse width m odulator mode.......... .............. .............. ......... 281 32.3.5.2. 9/10/11-bit pulse wi dth modulator mode............ ................ ......... 282 32.3.6. 16-bit pulse width modul ator mode........... ................. ................ ......... 283 32.4. watchdog timer mode ... .............. .............. .............. .............. .............. ......... 284 32.4.1. watchdog timer o peration .................. .............. .............. .............. ....... 284 32.4.2. watchdog timer usage ....... .............. .............. .............. .............. ......... 285 32.5. comparator clear function ... ................ ................ ................. .............. ......... 286 32.6. register descriptions for pc a0............. ................ ................. .............. ......... 288 33. c2 interface ............. ................ ................ ................. ................ ................. ........... 295 33.1. c2 interface registers........ ................. ................ ................. ................ ......... 295 33.2. c2 pin sharing ........ ................ ................ ................. .............. .............. ......... 298 document change list............... .............. .............. .............. .............. .............. ......... 299 contact information.......... ................. ................ ................ ................. .............. ......... 300 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 8 preliminary rev. 0.71 list of figures figure 1.1. c8051f392/3/6/7/8/9 bl ock diagram ........ ................. ................ ........... 18 figure 1.2. c8051f390/1/4/ 5 block diagram ......... .............. ............... ........... ......... 18 figure 1.3. c8051f370/1/4/ 5 block diagram ......... .............. ............... ........... ......... 19 figure 4.1. c8051f392/3/6/7/8/ 9 qfn-20 pinout diagram (top view) ................... 25 figure 4.2. c8051f390/1/ 4/5 pinout diagram (top view) ... ............... ........... ......... 26 figure 4.3. c8051f370/1/ 4/5 pinout diagram (top view) ... ............... ........... ......... 27 figure 5.1. qfn-20 package drawin g ...................... ................ ................. ............. 28 figure 5.2. qfn-20 recommended pcb land pattern ... .............. .............. ........... 29 figure 6.1. qfn-24 package drawin g ...................... ................ ................. ............. 30 figure 6.2. qfn-24 recommended pcb land pattern ... .............. .............. ........... 31 figure 7.1. normal mode digital supply curr ent vs. frequency ...... .............. ......... 44 figure 7.2. idle mode digita l supply current vs. frequency ..... ................. ............. 44 figure 9.1. adc0 functional blo ck diagram ............. ................ ................. ............. 48 figure 9.2. 10-bit adc track and conversion exampl e timing ........... ............ ...... 51 figure 9.3. adc0 equival ent input circuits ........ .............. .............. .............. ........... 52 figure 9.4. adc window compar e example: right-justified, single-ended data . 58 figure 9.5. adc window compar e example: left-justified, single-ended data .... 58 figure 9.6. adc0 multiplexer bl ock diagram ............ ................ ................. ............. 59 figure 10.1. temperature sensor transfer function .............. ............ ........... ......... 62 figure 10.2. temperature sensor error with 1-point calibrati on at 0 c ................ 63 figure 11.1. ida0 functional bl ock diagram ............ ................ ................. ............. 64 figure 11.2. ida1 functional bl ock diagram ............ ................ ................. ............. 65 figure 11.3. ida0 data word ma pping .............. .............. .............. .............. ........... 66 figure 12.1. voltage reference functional block diagram ..... ............ ........... ......... 71 figure 14.1. comparator0 function al block diagram ............. ............ ........... ......... 74 figure 14.2. comparator hysteresis plot ............... .............. ............... ........... ......... 75 figure 14.3. comparator input mu ltiplexer block diagram ...... ............ ........... ......... 78 figure 15.1. cip-51 block diagram .. ............... ................. .............. .............. ........... 80 figure 17.1. c8051f39x/37x memory map ................. ................. ................ ........... 91 figure 17.2. flash program memory map ............ .............. .............. .............. ......... 92 figure 19.1. sfr page stack ................. .............. .............. .............. .............. ....... 100 figure 19.2. sfr page stack while using sfr page 0x0f to access ts0cn .. 101 figure 19.3. sfr page stack after spi0 interrupt occurs ...... ............ ........... ....... 102 figure 19.4. sfr page stack upon pca interrupt occurrin g during a spi0 isr 103 figure 19.5. sfr page st ack upon return from pca0 inte rrupt ........... .............. 104 figure 19.6. sfr page st ack upon return from spi0 interr upt ............ .............. 105 figure 21.1. security byte decoding ............. ................ ................. .............. ......... 131 figure 22.1. slave address byte de finition ............... ................ ................. ........... 139 figure 22.2. write operatio n (single byte) ......... .............. .............. .............. ......... 140 figure 22.3. write operatio n (multiple bytes) .... .............. .............. .............. ......... 140 figure 22.4. current address read operati on (single byte) ......... .............. ......... 141 figure 22.5. current address read operati on (multiple bytes) ..... .............. ......... 142 figure 22.6. selective address r ead (single byte) .... ................. ................ ......... 143 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 9 c8051f39x/37x figure 22.7. selective address r ead (multiple bytes) ............ ............ ........... ....... 144 figure 23.1. crc0 block diagram .. ................ ................. .............. .............. ......... 145 figure 23.2. bit reverse register ................... ................. .............. .............. ......... 147 figure 24.1. reset sources ........ ................. ................ ................. ................ ......... 153 figure 24.2. power-on and vdd monitor re set timing ...... ............... ........... ....... 154 figure 26.1. oscillator op tions ............... .............. .............. .............. .............. ....... 162 figure 26.2. external crystal exam ple ................... .............. ............... ........... ....... 168 figure 27.1. port i/o f unctional block diagram ............... .............. .............. ......... 171 figure 27.2. port i/o cell block diagram ........... .............. .............. .............. ......... 172 figure 27.3. crossbar priority decoder - possible pin assign ments ......... ........... 176 figure 27.4. crossbar priority decoder example ...... ................ ................. ........... 177 figure 28.1. smbus0 block diagram ................. .............. .............. .............. ......... 190 figure 28.2. typical smbus confi guration ................ ................ ................. ........... 191 figure 28.3. smbus transaction ..... ................ ................. .............. .............. ......... 192 figure 28.4. typical smbus scl ge neration .............. ................. ................ ......... 194 figure 28.5. typical master writ e sequence .............. ................. ................ ......... 209 figure 28.6. typical mast er read sequence ......... .............. ............... ........... ....... 210 figure 28.7. typical slav e write sequence ........... .............. ............... ........... ....... 211 figure 28.8. typical slave read s equence ................ ................. ................ ......... 212 figure 29.1. uart0 block diagram ............ ................ ................. ................ ......... 218 figure 29.2. uart0 baud rate logi c ................ .............. .............. .............. ......... 219 figure 29.3. uart interconnect diagr am .............. .............. ............... ........... ....... 220 figure 29.4. 8-bit uart timing diagram ........... .............. .............. .............. ......... 220 figure 29.5. 9-bit uart timing diagram ........... .............. .............. .............. ......... 221 figure 29.6. uart multi-proce ssor mode interconnect diagram ......... ................ 222 figure 30.1. spi blo ck diagram ........... .............. .............. .............. .............. ......... 226 figure 30.2. multiple-master mo de connection diagram .......... ................. ........... 228 figure 30.3. 3-wire single master and 3-wi re single slave mode connection diagram .......... ................. .............. .............. .............. ......... 229 figure 30.4. 4-wire single master mode and 4-wire slave mode connection diagram .......... ................. .............. .............. .............. ......... 229 figure 30.5. master mode data/clo ck timing ............. ................. ................ ......... 231 figure 30.6. slave mode data/clock timing (ckpha = 0) ..... ............ ........... ....... 231 figure 30.7. slave mode data/clock timing (ckpha = 1) ..... ............ ........... ....... 232 figure 30.8. spi mast er timing (ckpha = 0) .... .............. .............. .............. ......... 236 figure 30.9. spi mast er timing (ckpha = 1) .... .............. .............. .............. ......... 237 figure 30.10. spi slave timing (c kpha = 0) ............. ................. ................ ......... 237 figure 30.11. spi slave timing (c kpha = 1) ............. ................. ................ ......... 238 figure 31.1. t0 mode 0 block diagr am .............. .............. .............. .............. ......... 244 figure 31.2. t0 mode 2 block diagr am .............. .............. .............. .............. ......... 245 figure 31.3. t0 mode 3 block diagr am .............. .............. .............. .............. ......... 246 figure 31.4. timer 2 16-bi t mode block diagram .. .............. ............... ........... ....... 251 figure 31.5. timer 2 8-bi t mode block diagram .. .............. .............. .............. ....... 252 figure 31.6. timer 2 low-fr equency oscillation capture mode blo ck diagram ... 253 figure 31.7. timer 3 16-bi t mode block diagram .. .............. ............... ........... ....... 257 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 10 preliminary rev. 0.71 figure 31.8. timer 3 8-bi t mode block diagram .. .............. .............. .............. ....... 258 figure 31.9. timer 3 low-fr equency oscillation capture mode blo ck diagram ... 259 figure 31.10. timer 4 16- bit mode block diagram .............. ............... ........... ....... 263 figure 31.11. timer 4 8-bi t mode block diagram .. .............. ............... ........... ....... 264 figure 31.12. timer 5 16- bit mode block diagram .............. ............... ........... ....... 268 figure 31.13. timer 5 8-bi t mode block diagram .. .............. ............... ........... ....... 269 figure 32.1. pca block diagram ..... ................ ................. .............. .............. ......... 273 figure 32.2. pca counter/timer bl ock diagram ......... ................. ................ ......... 274 figure 32.3. pca interrupt block diagram ................ ................ ................. ........... 275 figure 32.4. pca capture mode diagram .............. .............. ............... ........... ....... 277 figure 32.5. pca software time r mode diagram ....... ................. ................ ......... 278 figure 32.6. pca high-speed output mode diagram ...... .............. .............. ......... 279 figure 32.7. pca frequency output mode ............ .............. ............... ........... ....... 280 figure 32.8. pca 8-bit pwm mode diagram ......... .............. ............... ........... ....... 281 figure 32.9. pca 9, 10 and 11-bit pwm mode diagram .......... ................. ........... 282 figure 32.10. pca 16-bit pw m mode ........... ................ ................. .............. ......... 283 figure 32.11. pca module 2 wi th watchdog timer enabled .... ................. ........... 284 figure 32.12. comparator clear function diagram ........... .............. .............. ....... 286 figure 32.13. cexn with cpcen = 1, cpcpol = 0 ............. ............... ........... ....... 286 figure 32.14. cexn with cpcen = 1, cpcpol = 1 ............. ............... ........... ....... 287 figure 32.15. cexn with cpcen = 1, cpcpol = 0 ............. ............... ........... ....... 287 figure 32.16. cexn with cpcen = 1, cpcpol = 1 ............. ............... ........... ....... 287 figure 33.1. typical c2 pin shari ng .............. ................ ................. .............. ......... 298 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 11 c8051f39x/37x list of tables table 2.1. product selection guide ............... ................ ................. .............. ........... 20 table 3.1. c8051f33x replacement part numbers ...... ................. .............. ........... 21 table 4.1. pin definitions for t he c8051f39x/37x ....... ................. ................ ........... 22 table 5.1. qfn-20 package dimensi ons ............. .............. .............. .............. ......... 28 table 5.2. qfn-20 pcb land pattern dimensions .............. ............... ........... ......... 29 table 6.1. qfn-24 package dimensi ons ............. .............. .............. .............. ......... 30 table 6.2. qfn-24 pcb land pattern dimensions .............. ............... ........... ......... 31 table 7.1. absolute maximum ratings ............... .............. .............. .............. ........... 32 table 7.2. global electrical char acteristics ............ .............. ............... ........... ......... 33 table 7.3. port i/o dc elec trical characteristics .............. .............. .............. ........... 34 table 7.4. reset electrical characteristics ......... .............. .............. .............. ........... 35 table 7.5. flash electrical charac teristics ......... .............. .............. .............. ........... 36 table 7.6. eeprom electrical c haracteristics .......... ................ ................. ............. 36 table 7.7. internal high-frequency oscillator electrical char acteristics .... ............. 37 table 7.8. internal low-frequency oscillator electrical charac teristics .... ............. 37 table 7.9. internal low-power o scillator electrical characteri stics ........... ............. 37 table 7.10. adc0 electrical char acteristics ........... .............. ............... ........... ......... 38 table 7.11. adc temperature sensor electrical characteristics ..... .............. ......... 39 table 7.12. precision temperat ure sensor electrical charac teristics ....... ............. 39 table 7.13. voltage reference electrical charac teristics ....... ............ ........... ......... 40 table 7.14. voltage regulator elec trical characteristics ........ ............ ........... ......... 40 table 7.15. idac electrical char acteristics ............ .............. ............... ........... ......... 41 table 7.16. comparator electrical characteristics .... ................ ................. ............. 42 table 8.1. example temperature values in ts0dath:ts0datl ...... ........... ......... 45 table 15.1. cip-51 instruction set summary ............ ................ ................. ............. 82 table 19.1. sfr page stack ...... ................. ................ ................. ................ ........... 99 table 19.2. special function r egister (sfr) memory map .... ............ ........... ....... 109 table 19.3. special function regist ers .............. .............. .............. .............. ......... 110 table 20.1. configurable interrupt priority decoding .............. ............ ........... ....... 116 table 20.2. interrupt summary ... ................. ................ ................. ................ ......... 117 table 21.1. flash security summar y ................. .............. .............. .............. ......... 131 table 23.1. example 16-bit crc ou tputs ............ .............. .............. .............. ....... 146 table 27.1. port i/o assignment for analog functions ........... ............ ........... ....... 173 table 27.2. port i/o assignment for digital functions .......... ............... ........... ....... 174 table 27.3. port i/o assignmen t for external event trigger functions ................. 175 table 28.1. smbus clock source selection .............. ................ ................. ........... 194 table 28.2. minimum sda setup and hold times ...... ................. ................ ......... 195 table 28.3. sources for hardwa re changes to smbncn ......... ................. ........... 202 table 28.4. hardware address recognition examples (ehack = 1) .. ................. 203 table 28.5. smbus status decoding: hardware ack dis abled (ehack = 0) ...... 213 table 28.6. smbus status decoding: ha rdware ack enabled (ehack = 1) ...... 215 table 29.1. timer settings for standard baud rates using the internal 49 mhz o scillator ............ .............. .............. ......... 225 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 12 preliminary rev. 0.71 table 29.2. timer settings for standard baud rates using an external 22.1184 mhz oscillator ................ ................ ......... 225 table 30.1. spi slave timing para meters ......... .............. .............. .............. ......... 239 table 32.1. pca timebase input op tions ............ .............. .............. .............. ....... 274 table 32.2. pca0cpm and pca0 pwm bit settings for pca capture/compare modules ... ................. ................ ................. ........... 276 table 32.3. watchdog timer timeout intervals1 .. .............. .............. .............. ....... 285 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 13 c8051f39x/37x list of registers sfr definition 8.1. ts0 cn: temperature sensor control .... .............. .............. ........... 46 sfr definition 8.2. ts0dath: temperature sensor output hi gh byte .......... ............. 47 sfr definition 8.3. ts0datl: te mperature sensor ou tput low byte .... ........... ......... 47 sfr definition 9.1. adc0cf: adc0 configuration ........ ................ ................. ............. 53 sfr definition 9.2. adc0h: adc0 data word msb ...... ................ ................. ............. 54 sfr definition 9.3. adc0l: adc0 data word lsb ............... .............. .............. ........... 54 sfr definition 9.4. adc0cn : adc0 control ........... .............. .............. .............. ........... 55 sfr definition 9.5. adc0gth: a dc0 greater than data high by te ............. ............. 56 sfr definition 9.6. adc0gtl: adc0 greater-than data low byte ............... ............. 56 sfr definition 9.7. adc0lth: adc0 less-than data high byte ............ ........... ......... 57 sfr definition 9.8. adc0ltl: ad c0 less-than data low byte .. ........... ........... ......... 57 sfr definition 9.9. amx0p: amux 0 positive channel select ..... ............ ........... ......... 60 sfr definition 9.10. amx0n: am ux0 negative channel select ... ................. ............. 61 sfr definition 11.1. ida0cn: ida0 control ............ .............. .............. .............. ........... 67 sfr definition 11.2. ida0h: ida0 data word msb ....... ................ ................. ............. 68 sfr definition 11.3. ida0l: ida0 data word lsb ...... .............. ............... ........... ......... 68 sfr definition 11.4. ida1cn: ida1 control ............ .............. .............. .............. ........... 69 sfr definition 11.5. ida1h: ida1 data word msb ....... ................ ................. ............. 70 sfr definition 11.6. ida1l: ida1 data word lsb ...... .............. ............... ........... ......... 70 sfr definition 12.1. ref0cn: refe rence control ......... ................ ................. ............. 72 sfr definition 13.1. reg0cn: vo ltage regulator control .......... ............ ........... ......... 73 sfr definition 14.1. cpt0cn: com parator0 control ....... ................. ................ ........... 76 sfr definition 14.2. cpt0md: co mparator0 mode selection ....... ................. ............. 77 sfr definition 14.3. cpt0mx: co mparator0 mux selection ...... ............ ........... ......... 79 sfr definition 15.1. dpl: data po inter low byte ....... .............. ............... ........... ......... 86 sfr definition 15.2. dph: data pointer high byte .. .............. .............. .............. ........... 86 sfr definition 15.3. sp: stack pointe r ................. ................. .............. .............. ........... 87 sfr definition 15.4. acc: accumulator ........ ................. ................ ................. ............. 87 sfr definition 15.5. b: b r egister ............. .............. .............. .............. .............. ........... 88 sfr definition 15.6. psw: program status word .......... ................ ................. ............. 89 sfr definition 16.1. pfe0cn: pref etch engine control .. ................. ................ ........... 90 sfr definition 17.1. emi0 cn: external memory interface co ntrol .............. ................ 94 sfr definition 18.1. derivid: devi ce derivative id ... .............. ............... ........... ......... 95 sfr definition 18.2. revi sion: device revision id ................ ............... ........... ......... 96 sfr definition 18.3. sn3: serial number byte 3 ......... .............. ............... ........... ......... 96 sfr definition 18.4. sn2: serial number byte 2 ......... .............. ............... ........... ......... 97 sfr definition 18.5. sn1: serial number byte 1 ......... .............. ............... ........... ......... 97 sfr definition 18.6. sn0: serial number byte 0 ......... .............. ............... ........... ......... 98 sfr definition 19.1. sfrpage: sfr page ............ .............. .............. .............. ......... 106 sfr definition 19.2. sfrpgcn: sf r page control ...... ................ ................. ........... 107 sfr definition 19.3. sfrstack: sf r page stack ......... ................. ................ ......... 108 sfr definition 20.1. ie: in terrupt enable .............. ................. .............. .............. ......... 118 sfr definition 20.2. ip: inte rrupt priority ............ ................ ................. .............. ......... 119 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 14 preliminary rev. 0.71 sfr definition 20.3. iph: interrupt priority high .......... .............. ............... ........... ....... 120 sfr definition 20.4. eie1: extended interrupt enable 1 .............. ............ ........... ....... 121 sfr definition 20.5. eip1: extended interrupt priority 1 ........... ............... ........... ....... 122 sfr definition 20.6. eip1h: ext ended interrupt priority 1 high ... ............ ........... ....... 123 sfr definition 20.7. eie2: extended interrupt enable 2 .............. ............ ........... ....... 124 sfr definition 20.8. eip2: extended interrupt priority 2 ........... ............... ........... ....... 125 sfr definition 20.9. eip2h: ext ended interrupt priority 2 high ... ............ ........... ....... 125 sfr definition 20.10. it01c f: int0/int1 configurat ion .............. ............ ........... ....... 127 sfr definition 21.1. psctl: prog ram store r/w control ................ ................ ......... 135 sfr definition 21.2. flkey: flas h lock and key ............ ................. ................ ......... 136 sfr definition 21.3. flscl: flash scale ............. ................. .............. .............. ......... 137 sfr definition 23.1. crc0cn: crc0 control ............... ................ ................. ........... 148 sfr definition 23.2. crc0in: crc0 data input ............ ................ ................. ........... 149 sfr definition 23.3. crc0dat: crc0 data output ...... ................ ................. ........... 149 sfr definition 23.4. crc0auto: crc0 automatic control ........ ............ ........... ....... 150 sfr definition 23.5. crc0cnt: crc0 automatic flash sector count .......... ........... 151 sfr definition 23.6. crc0flip: crc0 bit flip .............. ................ ................. ........... 152 sfr definition 24.1. vdm0cn: vdd monitor control ...... ................. ................ ......... 156 sfr definition 24.2. rstsrc : reset source ......... .............. .............. .............. ......... 158 sfr definition 25.1. pcon: power control ............. .............. .............. .............. ......... 161 sfr definition 26.1. clksel: clock select ............ .............. .............. .............. ......... 163 sfr definition 26.2. oscicl: inte rnal h-f oscillator calibrati on ................ .............. 164 sfr definition 26.3. oscicn: inte rnal h-f oscillator control .. ............... ........... ....... 165 sfr definition 26.4. osclcn: inte rnal l-f oscillator control ..... ............ ........... ....... 166 sfr definition 26.5. oscxcn: exte rnal oscillator control ....... ............... ........... ....... 170 sfr definition 27.1. xbr0: port i/ o crossbar register 0 ......... ............... ........... ....... 179 sfr definition 27.2. xbr1: port i/ o crossbar register 1 ......... ............... ........... ....... 180 sfr definition 27.3. p0mask: port 0 mask register ..... ................ ................. ........... 181 sfr definition 27.4. p0mat: port 0 match register ... .............. ............... ........... ....... 182 sfr definition 27.5. p1mask: port 1 mask register ..... ................ ................. ........... 182 sfr definition 27.6. p1mat: port 1 match register ... .............. ............... ........... ....... 183 sfr definition 27.7. p0: port 0 .... .............. .............. .............. .............. .............. ......... 184 sfr definition 27.8. p0mdin: port 0 input mode ........... ................ ................. ........... 184 sfr definition 27.9. p0mdout: po rt 0 output mode .... ................ ................. ........... 185 sfr definition 27.10. p0skip: port 0 skip ........... ................. .............. .............. ......... 185 sfr definition 27.11. p1: port 1 .... ................ ................. ................ ................. ........... 186 sfr definition 27.12. p1mdin: port 1 input mode ......... ................ ................. ........... 186 sfr definition 27.13. p1mdout: po rt 1 output mode .... ................. ................ ......... 187 sfr definition 27.14. p1skip: port 1 skip ........... ................. .............. .............. ......... 187 sfr definition 27.15. p2: port 2 .... ................ ................. ................ ................. ........... 188 sfr definition 27.16. p2mdin: port 2 input mode ......... ................ ................. ........... 188 sfr definition 27.17. p2mdout: po rt 2 output mode .... ................. ................ ......... 189 sfr definition 27.18. p2skip: port 2 skip ........... ................. .............. .............. ......... 189 sfr definition 28.1. smb0cf: smbu s clock/configuration ........ ............ ........... ....... 196 sfr definition 28.2. smb1cf: smbu s clock/configuration ........ ............ ........... ....... 197 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 15 c8051f39x/37x sfr definition 28.3. smbtc: smbus timing and pi n control .............. .............. ....... 198 sfr definition 28.4. smb0cn: smbu s control .............. ................ ................. ........... 200 sfr definition 28.5. smb1cn: smbu s control .............. ................ ................. ........... 201 sfr definition 28.6. smb0 adr: smbus0 slave address ....... .............. .............. ....... 203 sfr definition 28.7. smb0adm: smbus0 slave address mask ........... .............. ....... 204 sfr definition 28.8. smb1 adr: smbus1 slave address ....... .............. .............. ....... 205 sfr definition 28.9. smb1adm: smbus1 slave address mask ........... .............. ....... 206 sfr definition 28.10. smb0dat: sm bus data .............. ................ ................. ........... 207 sfr definition 28.11. smb1dat: sm bus data .............. ................ ................. ........... 208 sfr definition 29.1. scon0: serial port 0 control ..... .............. ............... ........... ....... 223 sfr definition 29.2. sbuf0: seri al (uart0) port data buffer . ............... ........... ....... 224 sfr definition 30.1. spi0cfg: spi 0 configuration ....... ................ ................. ........... 233 sfr definition 30.2. spi0cn: spi0 control ............ .............. .............. .............. ......... 234 sfr definition 30.3. spi0ckr: spi 0 clock rate ........... ................ ................. ........... 235 sfr definition 30.4. spi0dat: spi0 data ........... ................. .............. .............. ......... 236 sfr definition 31.1. ckcon: clock control ............... .............. ............... ........... ....... 241 sfr definition 31.2. ckcon1: clock control 1 ............. ................ ................. ........... 242 sfr definition 31.3. tcon: timer c ontrol .............. .............. .............. .............. ......... 247 sfr definition 31.4. tmod: timer m ode ................ .............. .............. .............. ......... 248 sfr definition 31.5. tl0: timer 0 low byte ......... ................. .............. .............. ......... 249 sfr definition 31.6. tl1: timer 1 low byte ......... ................. .............. .............. ......... 249 sfr definition 31.7. th0: timer 0 high byte .............. .............. ............... ........... ....... 250 sfr definition 31.8. th1: timer 1 high byte .............. .............. ............... ........... ....... 250 sfr definition 31.9. tmr2cn: timer 2 control ............. ................ ................. ........... 254 sfr definition 31.10. tmr2rll: timer 2 reload regist er low byte ...... ........... ....... 255 sfr definition 31.11. tmr2rlh: timer 2 reload regi ster high byte .... ........... ....... 255 sfr definition 31.12. tmr2l: timer 2 low byte .... .............. .............. .............. ......... 255 sfr definition 31.13. tmr2h timer 2 high byte ........... ................ ................. ........... 256 sfr definition 31.14. tmr3cn: timer 3 control .... .............. .............. .............. ......... 260 sfr definition 31.15. tmr3rll: timer 3 reload regist er low byte ...... ........... ....... 261 sfr definition 31.16. tmr3rlh: timer 3 reload regi ster high byte .... ........... ....... 261 sfr definition 31.17. tmr3l: timer 3 low byte .... .............. .............. .............. ......... 261 sfr definition 31.18. tmr3h timer 3 high byte ........... ................ ................. ........... 262 sfr definition 31.19. tmr4cn: timer 4 control .... .............. .............. .............. ......... 265 sfr definition 31.20. tmr4rll: timer 4 reload regist er low byte ...... ........... ....... 266 sfr definition 31.21. tmr4rlh: timer 4 reload regi ster high byte .... ........... ....... 266 sfr definition 31.22. tmr4l: timer 4 low byte .... .............. .............. .............. ......... 266 sfr definition 31.23. tmr4h timer 4 high byte ........... ................ ................. ........... 267 sfr definition 31.24. tmr5cn: timer 5 control .... .............. .............. .............. ......... 270 sfr definition 31.25. tmr5rll: timer 5 reload regist er low byte ...... ........... ....... 271 sfr definition 31.26. tmr5rlh: timer 5 reload regi ster high byte .... ........... ....... 271 sfr definition 31.27. tmr5l: timer 5 low byte .... .............. .............. .............. ......... 271 sfr definition 31.28. tmr5h timer 5 high byte ........... ................ ................. ........... 272 sfr definition 32.1. pca0cn: pca c ontrol ........... .............. .............. .............. ......... 288 sfr definition 32.2. pca0md: pca mo de ............. .............. .............. .............. ......... 289 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 16 preliminary rev. 0.71 sfr definition 32.3. pca0pwm: pca pwm configuration ......... ............ ........... ....... 290 sfr definition 32.4. pca0clr: pc a comparator clear control .. ........... ........... ....... 291 sfr definition 32.5. pca0cpmn : pca capture/compare mode .. ................. ........... 292 sfr definition 32.6. pca0l: pca counter/timer low byte ........ ............ ........... ....... 293 sfr definition 32.7. pca0h: pca counter/timer high byte ....... ............ ........... ....... 293 sfr definition 32.8. pca0cpln: pca capture module low byte . ................. ........... 294 sfr definition 32.9. pca0cphn: pca capture module high byte ................ ........... 294 c2 register definition 33.1. c2ad d: c2 address ....... .............. ............... ........... ....... 295 c2 register definition 33.2. deviceid: c2 device id .............. ............... ........... ....... 296 c2 register definition 33.3. revid: c2 revision id ................. ............... ........... ....... 296 c2 register definition 33.4. fpctl: c2 flash programming control ... .............. ....... 297 c2 register definition 33.5. fpdat: c2 flas h programming data ....... .............. ....... 297 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 17 c8051f39x/37x 1. system overview c8051f39x/37x devices are fully integrated mixed-si gnal system-on-a-chip mcus. highlighted features are listed below. refer to section ?2 . ordering information? on page 20 for specific product feature selec- tion and part ordering numbers. ? high-speed pipelined 8051-compatible microcontroller core (up to 50 mips) ? in-system, full-speed, non-intrusive debug interface (on-chip) ? true 10-bit 500 ksps 20 or 16-channel single-ended/differential adc with analog multiplexer ? two 10-bit current output dacs ? precision temperature sensor with 2 c absolute accuracy ? precision programmable 49 mhz internal oscillator ? low-power, low-frequency oscillator ? 16 kb of on-chip flash memory ? 1024 bytes of on-chip ram ? co-packaged with 512 bytes of eeprom memory, accessible via i 2 c (c8051f37x) ? two smbus/i 2 c, uart, and spi serial interfaces implemented in hardware ? six general-purpose 16-bit timers ? programmable counter/timer array (pca) with three capture/compare modules and watchdog timer function ? on-chip power-on reset, v dd monitor, and temperature sensor ? on-chip voltage comparator ? 21 or 17 port i/o ? low-power suspend mode with fast wake-up time with on-chip power-on reset, v dd monitor, watchdog timer, and cl ock oscillator, the c8051f39x/37x devices are truly stand-alone system-on-a-chip solu tions. the flash memory can be reprogrammed even in-circuit, providing non-vo latile data storage, and also allowing field upgrades of th e 8051 firmware. user software has complete control of all peripherals, and ma y individually shut down any or all peripherals for power savings. the on-chip silicon labs 2- wire (c2) development interface allo ws non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. all analog and digi tal peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user functions, allowing in-system debugging with- out occupying package pins. the c8051f37x devices are specified for 1.8 to 3.6 v operation over the industrial temperature range (?40 to +85 c), while the c8051f39x devices operate over an extended temperature range (-40 to +105 c). the c8051f392/3/6/7/8/9 are available in a 20-pin qfn package and the c8051f390/1/4/5 and c8051f37x are available in a 24-pin qfn package. bo th package options are lead-free and rohs compli- ant. see section ?2. ordering information? on page 20 for ordering information. block diagrams are included in figure 1.1, figure 1.2 and figure 1.3. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 18 preliminary rev. 0.71 figure 1.1. c8051f392/3/6/7/8/9 block diagram figure 1.2. c8051f390/1/4/5 block diagram port 0 drivers digital peripherals uart timers 0 through 5 pca/ wdt 2xi2c / smbus priority crossbar decoder p0.0/vref p0.1/ida0 p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 crossbar control port i/o configuration cip-51 8051 controller core 16/8/4 kb isp flash program memory 256 byte sram sfr bus 768 byte xram port 1 drivers p1.0/ida1 p1.1 p1.2 p1.3 p1.4 p1.5 port 2 drivers p2.0/c2d spi analog peripherals comparator + - power net vdd gnd xtal1 sysclk system clock configuration external oscillator circuit precision 49 mhz oscillator debug / programming hardware power on reset reset c2d c2ck/rst 10-bit 500 ksps adc a m u x c8051f392/6/8 only xtal2 low-freq. oscillator p1.6 p1.7 ida0 cp0, cp0a 2 x 10-bit idacs ida1 internal ldo precision temperature sensor port 0 drivers digital peripherals uart timers 0 through 5 pca/ wdt 2xi2c / smbus priority crossbar decoder p0.0/vref p0.1/ida0 p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 crossbar control port i/o configuration cip-51 8051 controller core 16/8 kb isp flash program memory 256 byte sram sfr bus 768 byte xram port 1 drivers p1.0 p1.1 p1.2/ida1 p1.3 p1.4 p1.5 port 2 drivers p2.0 p2.1 p2.2 p2.3 p2.4/c2d spi analog peripherals comparator + - power net vdd gnd xtal1 sysclk system clock configuration external oscillator circuit precision 49 mhz oscillator debug / programming hardware power on reset reset c2d c2ck/rst 10-bit 500 ksps adc a m u x c8051f390/4 only xtal2 low-freq. oscillator p1.6 p1.7 ida0 cp0, cp0a 2 x 10-bit idacs ida1 internal ldo precision temperature sensor www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 19 c8051f39x/37x figure 1.3. c8051f370/1/4/5 block diagram port 0 drivers digital peripherals uart timers 0 through 5 pca/ wdt 2xi2c / smbus priority crossbar decoder p0.0/vref p0.1/ida0 p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7 crossbar control port i/o configuration cip-51 8051 controller core 16 kb isp flash program memory 256 byte sram sfr bus 768 byte xram port 1 drivers p1.0 p1.1 p1.2/ida1 p1.3 p1.4 p1.5 port 2 drivers p2.0 p2.1 p2.2/eescl p2.3/eesda p2.4/c2d spi analog peripherals comparator + - power net vdd gnd xtal1 sysclk system clock configuration external oscillator circuit precision 49 mhz oscillator debug / programming hardware power on reset reset c2d c2ck/rst 10-bit 500 ksps adc a m u x c8051f370/4 only xtal2 low-freq. oscillator p1.6 p1.7 ida0 cp0, cp0a 2 x 10-bit idacs ida1 internal ldo precision temperature sensor 512 byte i2c eeprom eesda eescl www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 20 preliminary rev. 0.71 2. ordering information the following features are common to all device in this family: ? 50 mips throughput (peak) ? 1 kb of ram (256 internal bytes and 768 xram bytes) ? calibrated internal 49 mhz oscillator ? internal 80 khz oscillator ? two smbus/i 2 c ? enhanced spi, enhanced uart ? six timers ? three programmable counter array channels ? analog comparator ? lead-free / rohs compliant table 2.1 shows the features that differentiate the devices in this family. table 2.1. product selection guide ordering part number flash memory (bytes) eeprom (bytes) digital port i/os 10-bit adc channels 10-bit dac channels on-chip voltage reference precision temperature sensor package 4x4 mm c8051f370-a-gm 16k 512 21 20 2 y y qfn-24 C8051F371-A-GM 16k 512 21 ? ? ? ? qfn-24 c8051f374-a-gm 8k 512 21 20 2 y y qfn-24 c8051f375-a-gm 8k 512 21 ? ? ? ? qfn-24 c8051f390-a-gm 16k ? 21 20 2 y y qfn-24 c8051f391-a-gm 16k ? 21 ? ? ? ? qfn-24 c8051f392-a-gm 16k ? 17 16 2 y y qfn-20 c8051f393-a-gm 16k ? 17 ? ? ? ? qfn-20 c8051f394-a-gm 8k ? 21 20 2 y y qfn-24 c8051f395-a-gm 8k ? 21 ? ? ? ? qfn-24 c8051f396-a-gm 8k ? 17 16 2 y y qfn-20 c8051f397-a-gm 8k ? 17 ? ? ? ? qfn-20 c8051f398-a-gm 4k ? 17 16 2 y y qfn-20 c8051f399-a-gm 4k ? 17 ? ? ? ? qfn-20 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 21 c8051f39x/37x 3. c8051f33x compatibility the c8051f39x/37x family is designed to be a pin and code compatible replacement for the c8051f33x device family, with an enhanced feature set. the c 8051f39x/37x device should function as a drop-in replacement for the c8051f33x devices in most app lications. table 3.1 lists recommended replacement part numbers for c8051f33x devices. see ?3.1. hardware incompatibilities? to determine if any changes are necessary when upgrading an existing c8051f33x design to the c8051f39x/37x. 3.1. hardware incompatibilities while the c8051f39x/37x family includes a number of new features not found on the c8051f33x family, there are some differences that should be considered for any design port. ? internal high-frequency oscillator : the undivided high-frequency oscillator on the c8051f39x/37x is 49 mhz, whereas the undivi ded high-frequency oscillator on the c8051f33x is 24.5 mhz. correspondingly, the internal high frequency divide ratios (ifcn) have doubled. thus, firmware written for the c8051f33x where the clksl[1:0] = 00b will result in the same sysclk frequency on the c8051f39x/37x. ? fabrication technology : the c8051f39x/37x is manufactured using a different technology process than the c8051f33x. as a result, many of the elec trical performance parameters will have subtle differences. these differences should not affect most systems but it is nonetheless important to review the electrical parameters for any blocks that are us ed in the design, and ensure they are compatible with the existing hardware. ? 5v tolerance : the port i/o pins on the c8501f39x/37x are not 5 v tolerant, whereas the port i/o pins on the c8051f33x are 5 v tolerant. ? lock byte address : the lock byte for c8051f39x/7x devices with 16 kb of flash resides at address 0x3fff, whereas the lock byte for c8051f33x devices with 16 kb of flash resides at address 0x3dff. the lock byte for c8051f39x/7x devices with 8 kb of flash resides at address 0x1fff, whereas the lock byte for c8051f33x devices with 8 kb of flash resides at address 0x1dff. table 3.1. c8051f33x replacement part numbers c8051f33x part number c8051f39x/37x part number c8051f330-gm c8051f396-a-gm c8051f331-gm c8051f397-a-gm c8051f332-gm c8051f398-a-gm c8051f333-gm c8051f399-a-gm c8051f334-gm c8051f398-a-gm c8051f335-gm c8051f399-a-gm c8051f336-gm c8051f392-a-gm c8051f337-gm c8051f393-a-gm c8051f338-gm c8051f390-a-gm c8051f339-gm c8051f391-a-gm www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 22 preliminary rev. 0.71 4. pin definitions table 4.1. pin definitions for the c8051f39x/37x name pin ?f392/3/6/ 7/8/9 pin ?f390/1/ 4/5 pin ?f370/1/ 4/5 type description v dd 3 4 4 power supply voltage. gnd 2 3 3 ground. this ground connection is required. the center pad may optionally be connected to ground also. rst / 4 5 5 d i/o device reset. open-drain output of internal por or v dd monitor. an external source can ini- tiate a system reset by driving this pin low for at least 10 s. c2ck d i/o clock signal for the c2 debug interface. c2d 5 6 6 d i/o bi-directional data signal for the c2 debug inter- face. shared with p2.0 on 20-pin packaging and p2.4 on 24-pin packaging. p0.0/ 1 2 2 d i/o or a in port 0.0. vref a in external vref input. p0.1 20 1 1 d i/o or a in port 0.1. ida0 a out ida0 output. p0.2/ 19 24 24 d i/o or a in port 0.2. xtal1 a in external clock input. this pin is the external oscillator return for a crystal or resonator. p0.3/ 18 23 23 d i/o or a in port 0.3. xtal2 a i/o or d in external clock output. for an external crystal or resonator, this pin is the excitation driver. this pin is the external cloc k input for cmos, capaci- tor, or rc oscilla tor configurations. p0.4 17 22 22 d i/o or a in port 0.4. p0.5 16 21 21 d i/o or a in port 0.5. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 23 c8051f39x/37x p0.6/ 15 20 20 d i/o or a in port 0.6. cnvstr d in adc0 external conv ert start or ida0 update source input. p0.7 14 19 19 d i/o or a in port 0.7. p1.0 13 ? ? d i/o or a in port 1.0. ida1 a out ida1 output. p1.0 18 18 d i/o or a in port 1.0. p1.1 12 17 17 d i/o or a in port 1.1. p1.2 - 16 16 d i/o or a in port 1.2. ida1 a out ida1 output. p1.2 11 ? ? d i/o or a in port 1.2. p1.3 10 15 15 d i/o or a in port 1.3. p1.4 9 14 14 d i/o or a in port 1.4. p1.5 8 13 13 d i/o or a in port 1.5. p1.6 7 12 12 d i/o or a in port 1.6. p1.7 6 11 11 d i/o or a in port 1.7. p2.0 5 10 10 d i/o or a in port 2.0. (also c2d on 20-pin packaging) p2.1 ? 9 9 d i/o or a in port 2.1. table 4.1. pin definitions for the c8051f39x/37x (continued) name pin ?f392/3/6/ 7/8/9 pin ?f390/1/ 4/5 pin ?f370/1/ 4/5 type description www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 24 preliminary rev. 0.71 p2.2 ? 8 ? d i/o or a in port 2.2. p2.2 - ? 8 d i/o or a in port 2.2. eescl d i/o eeprom scl connection. p2.3 ? 7 ? d i/o or a in port 2.3. p2.3 - ? 7 d i/o or a in port 2.3. eesda d i/o eeprom sda connection. p2.4 ? 6 6 d i/o port 2.4. (also c2d on 24-pin packaging) table 4.1. pin definitions for the c8051f39x/37x (continued) name pin ?f392/3/6/ 7/8/9 pin ?f390/1/ 4/5 pin ?f370/1/ 4/5 type description www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 25 c8051f39x/37x figure 4.1. c8051f392/3/6/7/8/9 qfn-20 pinout diagram (top view) 3 4 5 1 2 8 9 10 6 7 13 12 11 15 14 18 19 20 16 17 p0.0 gnd vdd /rst/c2ck p2.0/c2d p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 qfn-20 top view gnd (optional) www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 26 preliminary rev. 0.71 figure 4.2. c8051f390/1/4/5 pinout diagram (top view) 3 4 5 1 2 9 10 11 7 8 16 15 14 18 17 22 23 24 20 21 p0.0 gnd vdd /rst/c2ck p2.4/c2d p1.7 p1.6 p2.3 p2.2 p2.1 p1.2 p1.1 p1.0 p1.5 p1.4 p0.5 p0.4 p0.3 p0.2 p0.7 qfn-24 top view 6 12 p2.0 13 p1.3 19 p0.6 p0.1 gnd (optional) www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 27 c8051f39x/37x figure 4.3. c8051f370/1/4/5 pinout diagram (top view) 3 4 5 1 2 9 10 11 7 8 16 15 14 18 17 22 23 24 20 21 p0.0 gnd vdd /rst/c2ck p2.4/c2d p1.7 p1.6 p2.3/eesda p2.2/eescl p2.1 p1.2 p1.1 p1.0 p1.5 p1.4 p0.5 p0.4 p0.3 p0.2 p0.7 qfn-24 top view 6 12 p2.0 13 p1.3 19 p0.6 p0.1 gnd (optional) www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 28 preliminary rev. 0.71 5. qfn-20 package specifications figure 5.1. qfn-20 package drawing table 5.1. qfn-20 package dimensions dimension min typ max dimension min typ max a 0.80 0.85 0.90 l 0.50 0.55 0.60 a1 0.00 0.035 0.05 aaa ? ? 0.10 b 0.20 0.25 0.30 bbb ? ? 0.10 d 4.00 bsc. ccc ? ? 0.08 d2 2.00 2.10 2.20 ddd ? ? 0.10 e 0.50 bsc. eee ? ? 0.10 e 4.00 bsc. ggg 0.05 e2 2.00 2.10 2.20 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vggd except for custom features d2, e2, z, y, and l wh ich are toleranced per supplier designation. 4. recommended card reflow profile is per the je dec/ipc j-std-020c specification for small body components. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 29 c8051f39x/37x figure 5.2. qfn-20 recommended pcb land pattern table 5.2. qfn-20 pcb land pattern dimensions dimension max dimension max c1 3.80 x2 2.20 c2 3.80 y1 1.00 e 0.50 y2 2.20 x1 0.30 notes: general 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. solder mask design 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 5. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 8. a 2x2 array of 0.95mm openings on a 1.1 mm pitc h should be used for the center pad to assure the proper paste volume (71% paste coverage). card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 30 preliminary rev. 0.71 6. qfn-24 package specifications figure 6.1. qfn-24 package drawing table 6.1. qfn-24 package dimensions dimension min typ max dimension min typ max a 0.70 0.75 0.80 l 0.30 0.40 0.50 a1 0.00 0.02 0.05 l1 0.00 ? 0.15 b 0.18 0.25 0.30 aaa ? ? 0.15 d 4.00 bsc. bbb ? ? 0.10 d2 2.55 2.70 2.80 ddd ? ? 0.05 e 0.50 bsc. eee ? ? 0.08 e 4.00 bsc. z ? 0.24 ? e2 2.55 2.70 2.80 y ? 0.18 ? notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec solid state outline mo-220, variation wggd except for custom features d2, e2, z, y, and l wh ich are toleranced per supplier designation. 4. recommended card reflow profile is per the je dec/ipc j-std-020c specification for small body components. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 31 c8051f39x/37x figure 6.2. qfn-24 recommended pcb land pattern table 6.2. qfn-24 pcb land pattern dimensions dimension min max dimension min max c1 3.90 4.00 x2 2.70 2.80 c2 3.90 4.00 y1 0.65 0.75 e 0.50 bsc y2 2.70 2.80 x1 0.20 0.30 notes: general 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 4. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. a 2 x 2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch should be used for the center pad. card assembly 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per the jedec/ipc j-std- 020c specification for small body components. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 32 preliminary rev. 0.71 7. electrical characteristics 7.1. absolute m aximum specifications table 7.1. absolute maximum ratings parameter condition min typ max unit ambient temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on any port i/o pin or rst with respect to gnd ?0.3 ? v dd + 0.3 v voltage on v dd with respect to gnd ?0.3 ? 4.2 v maximum total current through v dd or gnd ? ? 100 ma maximum output current sunk by rst or any port pin ??100ma note: stresses above those listed under ?absolute maximu m ratings? may cause permanent damage to the device. this is a stress rating only and functional operat ion of the devices at thos e or any other conditions above those indicated in the operation listings of this sp ecification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 33 c8051f39x/37x 7.2. electrical characteristics table 7.2. global electrical characteristics ?40 to +105 c (c8051f39x), ?40 to +85 c (c8051f37x), 50 mhz system clock, unless otherwise specified. parameter condition min typ max unit supply voltage (v dd ) normal operation v rst 1 3.0 3.6 v writing or erasing flash memory 1.8 3.0 3.6 v digital supply ram data retention voltage ?1.5? v sysclk (system clock) 2 0?50mhz t sysh (sysclk high time) 9.5 ? ? ns t sysl (sysclk low time) 9.5 ? ? ns specified operating temperature range c8051f39x ?40 ? +105 c c8051f37x ?40 ? +85 c digital supply current?cpu active (normal mode, fetching instructions from flash) i dd 3 v dd = 3.6 v, f = 50 mhz ? 7.1 10.5 ma v dd = 3.0 v, f = 50 mhz ? 7.0 10.4 ma v dd = 3.6 v, f = 25 mhz ? 4.6 6.5 ma v dd = 3.0 v, f = 25 mhz ? 4.5 6.4 ma v dd = 3.6 v, f = 1 mhz ? 0.35 ? ma v dd = 3.0 v, f = 1 mhz ? 0.35 ? ma v dd = 3.0 v, f = 80 khz ? 0.25 ? ma digital supply current?cpu inactive (idle mode , not fetching instructions from flash) i dd 3 v dd = 3.6 v, f = 50 mhz ? 3.9 4.5 ma v dd = 3.0 v, f = 50 mhz ? 3.8 4.4 ma v dd = 3.6 v, f = 25 mhz ? 2.1 2.5 ma v dd = 3.0 v, f = 25 mhz ? 2.0 2.4 ma v dd = 3.6 v, f = 1 mhz ? 0.15 ? ma v dd = 3.0 v, f = 1 mhz ? 0.15 ? ma v dd = 3.0 v, f = 80 khz ? 0.1 ? ma digital supply current (suspend mode) oscillator not running, v dd monitor disabled, regulator running (stopcf = 0) ?77?a digital supply current (stop mode) oscillator not running, v dd monitor disabled, regulator running (stopcf = 0) ?81?a digital supply current (stop mode, regulator shut- down) oscillator not running, v dd monitor disabled, regulator shutdown (stopcf = 1) ?0.2?a notes: 1. given in table 7.4 on page 35. 2. sysclk must be at least 32 khz to enable debugging. 3. based on device characterization data; not production tested. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 34 preliminary rev. 0.71 table 7.3. port i/o dc electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +105 c (c8051f39x), ?40 to +85 c (c8051f37x), unless otherwise specified. parameters condition min typ max unit standard port i/o output high voltage i oh = ?3 ma, port i/o push-pull v dd ?0.7 ? ? v i oh = ?10 a, port i/o push-pull v dd ?0.1 ? ? v i oh = ?10 ma, port i/o push-pull ? v dd ?0.8 ? v output low voltage i ol =8.5ma ? ? 0.6 v i ol =10a ? ? 0.1 v i ol =10ma, 1.8v v dd < 2.7 v ? 0.8 ? v i ol =25ma, 2.7v v dd 3.6 v ? 1.0 ? v input high voltage 1.8 v v dd < 2.7 v v dd ?0.4 ? ? v 2.7 v v dd 3.6 v v dd ?0.5 ? ? v input low voltage 1.8 v v dd < 2.7 v ? ? 0.5 v 2.7 v v dd 3.6 v ? ? 0.6 v input leakage current weak pullup off ? ? 1 a weak pullup on, v in = 0 v ? 20 100 a eesda and eescl (c8051f37x only)* output low voltage (eesda) i ol =0.15ma, v dd = 1.8 v ? ? 0.2 v output low voltage (eesda) i ol =2.1ma, v dd =3v ? ? 0.4 v output leakage current (eesda) eepue = 0, v dd =3.6v, 0v v out v dd ?? 2a input high voltage v dd x 0.7 ? ? v input low voltage ? ? v dd x 0.3 v input leakage current eepue = 0, standby, v dd =3.6v, 0v v in v dd ??3a note: applicable when interfacing to the c8051f37x eeprom. otherwise, standard port i/o characteristics apply. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 35 c8051f39x/37x table 7.4. reset electrical characteristics ?40 to +105 c (c8051f39x), ?40 to +85 c (c8051f37x), unless otherwise specified. parameter condition min typ max unit rst output low voltage i ol =4ma, v dd = 1.8 v to 3.6 v ??0.6v rst input low voltage ? ? 0.6 v rst input pullup current rst = 0.0 v ? 20 100 a v dd por threshold (v rst )v rst_low 1.7 1.75 1.8 v v rst_high 2.4 2.55 2.7 v missing clock detector time- out time from last system clock rising edge to reset initiation 80 580 800 s reset time delay delay between release of any reset source and code execution at location 0x0000 ??40s minimum rst low time to generate a system reset 15 ? ? s v dd monitor turn-on time 100 ? ? s v dd monitor supply current ? 20 50 a www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 36 preliminary rev. 0.71 table 7.5. flash electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +105 c (c8051f39x), ?40 to +85 c (c8051f37x), unless otherwise specified. parameter condition min typ max unit flash size c8051f390/1/2/3, c8051f370/1 16384 bytes c8051f394/5/6/7, c8051f374/5 8192 bytes c8051f398/9 4096 bytes endurance 20000 100000 ? erase/write erase cycle time 23 25 27 ms write cycle time 58 61 64 s table 7.6. eeprom electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +85 c (c8051f37x), unless otherwise specified. parameter condition min typ max unit eeprom size c8051f37x 512 bytes endurance 1000000 ? ? write cycles write cycle time ? ? 3.5 ms eescl clock frequ ency ? ? 400 khz supply current v dd = 3.6 v, standby ? ? 3 a v dd = 3.6 v, read ? ? 2 ma v dd =3.6v, write ? ? 3 ma www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 37 c8051f39x/37x table 7.7. internal high-frequency oscillator electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +105 c (c8051f39x), ?40 to +8 5 c (c8051f37x), using factory-calibrated settings, unless otherwise specified. parameter condition min typ max unit oscillator frequency ifcn = 11b 48 49 50 mhz oscillator supply current (from v dd ) 25 c, v dd =3.0v, oscicn.7 = 1, ocsicn.5 = 0 ? 840 880 a power supply sensitivity constant temperature ? 0.12 ? %/v temperature sensitivity constant supply ? 90 ? ppm/c table 7.8. internal low-frequency oscillator electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +105 c (c8051f39x), ?40 to +8 5 c (c8051f37x), using factory-calibrated settings, unless otherwise specified. parameter condition min typ max unit oscillator frequency oscld = 11b 75 80 85 khz oscillator supply current (from v dd ) 25 c, v dd =3.0v, osclcn.7 = 1 ?5.512 a power supply sensitivity constant temperature ? 0.05 ? %/v temperature sensitivity constant supply ? 160 ? ppm/c table 7.9. internal low-power oscillator electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +105 c (c8051f39x), ?40 to +85 c (c8051f37x), using factory-calibrated settings, unless otherwise specified. parameter condition min typ max unit oscillator frequency 18.5 20 21.5 mhz power supply sensitivity con stant temperature ? 0.1 ? %/v temperature sensitivity constant supply ? 60 ? ppm/c www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 38 preliminary rev. 0.71 table 7.10. adc0 electrical characteristics v dd = 3.0 v, vref = 2.40 v (refsl = 0), ?40 to +105 c (c8051f39x), ?40 to +85 c (c8051f37x), unless otherwise specified. parameter condition min typ max unit dc accuracy resolution 10 bits integral nonlinearity ? <0.5 2.0 lsb differential nonlinearity guara nteed monotonic ? <0.5 1 lsb offset error ?2 0 2 lsb full scale error ?5 ?2 1 lsb offset temperature coefficient ? 0.005 ? lsb/c dynamic performance (10 khz sine-wave single-ended input, 1 db below full scale, 500 ksps) signal-to-noise plus distortion 55 58 ? db total harmonic distortion up to the 5th harmonic ? ?73 ? db spurious-free dynamic range ? 68 ? db conversion rate sar conversion clock ? ? 8.33 mhz conversion time in sar clocks 13 ? ? clocks track/hold acquisition time 300 ? ? ns throughput rate ? ? 500 ksps analog inputs adc input voltage range single ended (ain+ ? gnd) 0 ? vref v differential (ain+ ? ain?) ?vref ? vref v absolute pin voltage with respect to gnd single ended or differential 0 ? v dd v sampling capacitance (c sam- ple ) ?5?pf input multiplexer impedance (r mux ) ?1.6? k ? power specifications power supply current (v dd supplied to adc0) operating mode, 500 ksps ? 860 1010 a power supply rejection single ended (ain+ ? gnd) ? 1.15 ? mv/v differential (ain+ ? ain?) ? 2.45 ? mv/v www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 39 c8051f39x/37x table 7.11. adc temperature sensor electrical characteristics v dd = 3.0 v, ?40 to +105 c (c8051f39x), ?40 to +85 c (c8051f37x), unless otherwise specified. parameter condition min typ max unit linearity ? 0.75 ? c slope ? 2.92 ? mv/c slope error* ? 70 ? v/c offset temp = 0 c ? 785 ? mv offset error* temp = 0 c ? 13 ? mv supply current ? 90 120 a note: represents one standard deviation from the mean. table 7.12. precision temperature sensor electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +105 c (c8051f39x), ?40 to +85 c (c8051f37x), unless otherwise specified. parameter condition min typ max unit range ?40 ? 105 c absolute error ?2 0 +2 c integral nonlinearity ? 0 0.8 c resolution 0.0078125 c power supply reje ction ? 0.05 0.2 c/v supply current ? 230 280 a clock frequency (f ts0 ) 320 520 730 khz www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 40 preliminary rev. 0.71 table 7.13. voltage reference electrical characteristics v dd = 3.0 v, ?40 to +105 c (c8051f39x), ?40 to +8 5 c (c8051f37x), unless otherwise specified. parameter condition min typ max unit internal reference (refbe = 1) output voltage 2.4 v setting 2.37 2.4 2.43 v 1.2 v setting 1.18 1.2 1.22 v vref short-circuit current ? ? 8 ma vref temperature coefficient ? 33 ? ppm/c load regulation load = 0 to 200 a to agnd ? 6 ? v/a vref turn-on time 1 4.7 f tantalum, 0.1 f ceramic bypass ? 1.5 ? ms vref turn-on time 2 0.1 f ceramic bypass ? 110 ? s power supply rejection 2.4 v setting ? 3.5 ? mv/v 1.2 v setting ? 1.1 ? mv/v external reference (refbe = 0) input voltage range 1.0 ? v dd v input current sample rate = 200 ksps; vref = 3.0 v ? 3 ? a power specifications supply current refbe = ?1? or tempe = ?1? ? 70 100 a table 7.14. voltage regulator electrical characteristics v dd = 3.0 v, ?40 to +105 c (c8051f39x), ?40 to +8 5 c (c8051f37x), unless otherwise specified. parameter condition min typ max unit output voltage 1.73 1.78 1.83 v power supply sensitivity con stant temperature ? 0.5 ? %/v temperature sensitivity constant supply ? 55 ? ppm/c www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 41 c8051f39x/37x table 7.15. idac electrical characteristics v dd = 3.0 v, ?40 to +105 c (c8051f39x), ?40 to +85 c (c8051f37x), full-scale output current set to 2 ma, unless otherwise specified. parameter condition min typ max unit static performance resolution 10 bits integral nonlinearity ? <1 3 lsb differential nonlinearity 0 to +105 c , guaranteed monotonic ? <0.5 1 lsb ?40 to 0c ? <0.5 1.3 lsb output compliance range 0 ? v dd ? 1.0 v offset error ? 0 ? a full scale error 2 ma full scale output current tbd 0 tbd a 1 ma full scale output current tbd 0 tbd a 0.5 ma full scale output current tbd 0 tbd a full scale error tempco ? 80 ? ppm/c v dd power supply rejection ratio ? 1.05 ? a/v dynamic performance output settling time to 1/2 lsb ida0h:l = 0x3ff to 0x000 ? 7 ? s startup time ? 6.5 ? s gain variation 1 ma full scale output current ? tbd ? % 0.5 ma full scale output current ? tbd ? % power consumption power supply current (v dd supplied to idac) 2 ma full scale output current ? 2065 ? a 1 ma full scale output current ? 1065 ? a 0.5 ma full scale output current ? 565 ? a www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 42 preliminary rev. 0.71 table 7.16. comparator electrical characteristics v dd = 3.0 v, ?40 to +105 c (c8051f39x), ?40 to +85 c (c8051f37x), unless otherwise specified. parameter condition min typ max unit response time mode 0, vcm* = 1.5 v cp0+ ? cp0? = 100 mv ? 370 ? ns cp0+ ? cp0? = ?100 mv ? 135 ? ns response time mode 3, vcm* = 1.5 v cp0+ ? cp0? = 100 mv ? 1575 ? ns cp0+ ? cp0? = ?100 mv ? 3705 ? ns common-mode rejection ratio ? 0.6 5 mv/v positive hysteresis mode 0 (cpmd = 00) cp0hyp1?0 = 00 ? 0.5 ? mv cp0hyp1?0 = 01 ? 8 ? mv cp0hyp1?0 = 10 ? 16 ? mv cp0hyp1?0 = 11 ? 32 ? mv negative hysteresis mode 0 (cpmd = 00) cp0hyn1?0 = 00 ? 0.5 ? mv cp0hyn1?0 = 01 ? ?8 ? mv cp0hyn1?0 = 10 ? ?16 ? mv cp0hyn1?0 = 11 ? ?32 ? mv positive hysteresis mode 1 (cpmd = 01) cp0hyp1?0 = 00 ? 0.5 ? mv cp0hyp1?0 = 01 ? 6 ? mv cp0hyp1?0 = 10 ? 12 ? mv cp0hyp1?0 = 11 ? 24.5 ? mv negative hysteresis mode 1 (cpmd = 01) cp0hyn1?0 = 00 ? 0.5 ? mv cp0hyn1?0 = 01 ? ?6 ? mv cp0hyn1?0 = 10 ? ?12 ? mv cp0hyn1?0 = 11 ? ?24.5 ? mv positive hysteresis mode 2 (cpmd = 10) cp0hyp1?0 = 00 ? 0.7 ? mv cp0hyp1?0 = 01 ? 4.5 ? mv cp0hyp1?0 = 10 ? 10 ? mv cp0hyp1?0 = 11 ? 19 ? mv negative hysteresis mode 2 (cpmd = 10) cp0hyn1?0 = 00 ? 0.7 ? mv cp0hyn1?0 = 01 ? ?4.5 ? mv cp0hyn1?0 = 10 ? ?10 ? mv cp0hyn1?0 = 11 ? ?19 ? mv positive hysteresis mode 3 (cpmd = 11) cp0hyp1?0 = 00 ? 1.6 2.3 mv cp0hyp1?0 = 01 2 4 6 mv cp0hyp1?0 = 10 4.8 8 11 mv cp0hyp1?0 = 11 10 15.5 21 mv www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 43 c8051f39x/37x negative hysteresis mode 3 (cpmd = 11) cp0hyn1?0 = 00 ? 1.6 2.3 mv cp0hyn1?0 = 01 ?6 ?4 ?2 mv cp0hyn1?0 = 10 ?11 ?8 ?4.8 mv cp0hyn1?0 = 11 ?21 ?15.5 ?10 mv inverting or non-inverting input voltage range ?0.25 ? v dd + 0.25 v input capacitance ? 4 ? pf input bias current ? 0.001 ? na input offset voltage 10 ? ?10 mv power supply power supply rejection ? 0.1 ? mv/v power-up time ? 6.5 ? s supply current at dc mode 0 ? 32 48 a mode 1 ? 15 20 a mode 2 ? 5 10 a mode 3 ? 2 8 a note: vcm is the common-mode voltage on cp0+ and cp0?. table 7.16. comparator electrical characteristics (continued) v dd = 3.0 v, ?40 to +105 c (c8051f39x), ?40 to +85 c (c8051f37x), unless otherwise specified. parameter condition min typ max unit www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 44 preliminary rev. 0.71 7.3. typical performance curves figure 7.1. normal mode digital supply current vs. frequency figure 7.2. idle mode digital supply current vs. frequency 5.0 6.0 7.0 8.0 vdd=1.8v vdd=3.0v vdd=3.6v f > 9 mhz oneshot disabled f < 9 mhz oneshot enabled 0.0 1.0 2.0 3.0 4.0 0 5 10 15 20 25 30 35 40 45 50 idd(ma) sysclk(mhz) 2.5 3.0 3.5 4.0 vdd=1.8v vdd=3.0v vdd=3.6v 0.0 0.5 1.0 1.5 2.0 0 5 10 15 20 25 30 35 40 45 50 idd(ma) sysclk(mhz) www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 45 c8051f39x/37x 8. precision te mperature sensor (c8051f390/2/4/6/8 an d c8051f370/4 only) the precision temperature sensor is a self-contained module that reports the die temperature in degrees celsius. for the temperature sensor accessed by the adc, refer to section 10. the precision temperature sensor begins a conversion once the ts0strt bit is set to 1 then cleared to 0 by firmware. the conversion length is specified by ts0cnvl, with a longer conv ersion time resulting in a more accurate temperature measurement. the ts0dn bit is set by hardware once the temperature sensor block has completed the measurement, and the temperature is available in ts0dath:ts0datl. the precision temperature sensor may also be enable d as an interrupt source by setting the epts bit in eie2. when enabled, the interrupt occurs once ts0dn is set to 1 by hardware. 8.1. temperature in two?s complement the 16-bit word in ts0dath:ts0datl is the temper ature in degrees celsius represented in two's com- plement with 1 weighted sign bit, 8 integer bits, and 7 fractional bits. equation 8.1 converts the value in ts0dath:ts0datl from two?s complement binary to decimal. equation 8.1. temperature conversion from two?s complement binary to decimal where: ? ts0dath[n] is the n th bit in ts0dath ? ts0datl[n] is the n th bit in ts0datl table 8.1 lists several 16-bit values in ts0dath:ts0datl and the corresponding temperature. table 8.1. example temperature values in ts0dath:ts0datl hexadecimal binary temperature (c) 0x3480 0011 0100 1000 0000 105 0x1400 0001 0100 0000 0000 40 0x0ce0 0000 1100 1110 0000 25.75 0x0080 0000 0000 1000 0000 1 0x0040 0000 0000 0100 0000 0.5 0x0001 0000 0000 0000 0001 1/128 0x0000 0000 0000 0000 0000 0 0xffff 1111 1111 1111 1111 ?1/128 0xffc0 1111 1111 1100 0000 ?0.5 0xff80 1111 1111 1000 0000 ?1 0xf320 1111 0011 0010 0000 ?25.75 0xec00 1110 1100 0000 0000 ?40 temperature in ? cts 0 dath 7 ?? 2 8 ? ?? ? ts 0 dath n ?? 2 n 1 + ? ts 0 datl n ?? 2 n 7 ? ? n 0 = 7 ? + n 0 = 6 ? ?? ?? ?? ?? + = www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 46 preliminary rev. 0.71 sfr address = 0xd2; sfr page = f sfr definition 8.1. ts0cn: te mperature sensor control bit76543210 name ts0strt ts0dn ts0cnvl type r/w r r/w r/w r/w r/w reset 00000000 bit name function 7 ts0strt temperature sensor start. firmware must set this bit to 1, then clear this bit to 0 to start a temperature sensor measurement. 6ts0dn temperature sensor finished flag. hardware will set ts0dn to 1 when a tem perature sensor me asurement is com- plete. if enabled, a temperature sensor in terrupt will be generated. this bit must be cleared to 0 by firmware. 5:3 reserved must write 000b. 2:0 ts0cnvl temperature sensor conversion length. this field sets the conversion length of time over which the temperature is calcu- lated. a longer conversion length results in a more accurate measurement. the conversion length in microseconds is derived from the following equation, where ts0cnvl is the 3-bit value held in ts0cnvl[2:0] and f ts0 is the precision tem- perature sensor clock frequency given in table 7.12. conversion length in ? s 256 f ts 0 ----------- 10 6 ? ?? ?? 2 ts 0 cnvl 1 + 1 + ?? ? 32 + = www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 47 c8051f39x/37x sfr address = 0xd3; sfr page = 0 sfr address = 0xd2; sfr page = 0 sfr definition 8.2. ts0dath: temp erature sensor output high byte bit76543210 name ts0dath type r/w reset 00000000 bit name function 7:0 ts0dath temperature sensor data word (msb). this byte represents the msb of the temperature sensor data word. the data word is a 16-bit, 2?s complement num- ber. sfr definition 8.3. ts0datl: temp erature sensor output low byte bit76543210 name ts0datl type r/w reset 00000000 bit name function 7:0 ts0datl temperature sensor data word (lsb). this byte represents the lsb of the temperature sensor data word. the data word is a 16-bit, 2?s complement num- ber. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 48 preliminary rev. 0.71 9. 10-bit adc (adc0, c8051f390 /2/4/6/8 and c8051f370/4 only) adc0 on the c8051f390/2/4/6/8 and c8051f370/4 is a 500 ksps, 10-bit successive-approximation-regis- ter (sar) adc with integrated track-and-hold and a programmable window detector. the adc is fully con- figurable under software control via special function registers. the adc may be configured to measure various different signals using the analog multiplexe r described in section ?9.4 . adc0 analog multiplexer (c8051f390/2/4/6/8 and c8051f370/4 only)? on page 59 . the voltage reference for the adc is selected as described in section ?12. voltage reference options? on page 71. the adc0 subsystem is enabled only when the ad0en bit in the ad c0 control register (a dc0cn) is set to logic 1. the adc0 subsystem is in low power shutdown when this bit is logic 0. figure 9.1. adc0 functional block diagram adc0cf ad0ljst ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 10-bit sar adc ref sysclk adc0h 32 adc0cn ad0cm0 ad0cm1 ad0cm2 ad0wint ad0busy ad0int ad0tm ad0en timer 0 overflow timer 2 overflow timer 1 overflow start conversion 000 ad0busy (w) vdd adc0lth ad0wint 001 010 011 100 cnvstr input window compare logic gnd 101 timer 3 overflow adc0ltl adc0gth adc0gtl adc0l amx0p amx0p5 amx0p4 amx0p3 amx0p2 amx0p1 amx0p0 amx0n amx0n5 amx0n4 amx0n3 amx0n2 amx0n1 amx0n0 ain+ ain- vref positive input (ain+) amux vdd negative input (ain-) amux temp sensor port i/o pins* port i/o pins* * 20 selections on 24-pin package 16 selections on 20-pin package timer 4 overflow timer 5 overflow 110 111 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 49 c8051f39x/37x 9.1. output code formatting the conversion code format differs between single -ended and differential modes. the registers adc0h and adc0l contain the high and low bytes of the outpu t conversion code from the adc at the completion of each conversion. data can be right-justified or left -justified, depending on the setting of the ad0ljst bit (adc0cn.0). when in single-ended mode, conversion codes are represented as 10-bit unsigned integers. inputs are measured from 0 to vref x 1023/1024. ex ample codes are shown belo w for both right-justified and left-justified data. unused bits in the adc0h and adc0l registers are set to 0. when in differential mode, conversion codes are re presented as 10-bit signed 2s complement numbers. inputs are measured from ?vref to vref x 511/512. example codes are shown below for both right-jus- tified and left-justified data. for right-justified data, the unused msbs of adc0h are a sign-extension of the data word. for left-justified data, the unused lsbs in the adc0l register are set to 0. input voltage (single-ended) right-justified adc0h:adc0l (ad0ljst = 0) left-justified adc0h:adc0l (ad0ljst = 1) vref x 1023/1024 0x03ff 0xffc0 vref x 512/1024 0x0200 0x8000 vref x 256/1024 0x0100 0x4000 0 0x0000 0x0000 input voltage (differential) right-justified adc0h:adc0l (ad0ljst = 0) left-justified adc0h:adc0l (ad0ljst = 1) vref x 511/512 0x01ff 0x7fc0 vref x 256/512 0x0100 0x4000 0 0x0000 0x0000 ?vref x 256/512 0xff00 0xc000 ?vref 0xfe00 0x8000 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 50 preliminary rev. 0.71 9.2. modes of operation adc0 has a maximum conversion speed of 500 ksps. the adc0 conversion clock is a divided version of the system clock, determined by the ad0sc bits in the adc0cf register. 9.2.1. starting a conversion a conversion can be initiated in one of several ways, depending on the programmed states of the adc0 start of conversion mode bits (ad0cm2 ? 0) in register adc0cn. conver sions may be initiated by one of the following: 1. writing a 1 to the ad0busy bit of register adc0cn 2. a timer 0 overflow (i.e., ti med continuous conversions) 3. a timer 2 overflow 4. a timer 1 overflow 5. a rising edge on the cnvstr input signal 6. a timer 3 overflow 7. a timer 4 overflow 8. a timer 5 overflow writing a 1 to ad0busy provides software contro l of adc0 whereby conversions are performed "on- demand". during conversion, the ad0busy bit is set to logic 1 and reset to logic 0 when the conversion is complete. the falling edge of ad0bu sy triggers an interrupt (when enabl ed) and sets the adc0 interrupt flag (ad0int). note: when polling for adc conversi on completions, the adc0 interrupt flag (ad0int) should be used. converted data is available in th e adc0 data registers, adc0h:adc0l, when bit ad0int is logic 1. note that when timer 2, 3, 4, or 5 overfl ows are used as the conversion source, low byte over- flows are used if the timer is in 8-bit mode; high byte overflows are used if the timer is in 16-bit mode. see section ?31. timers? on page 240 for timer configuration. important note about using cnvstr: the cnvstr input pin also functions as a port i/o pin. when the cnvstr input is used as t he adc0 conversion source, the associated pin should be skipped by the digi- tal crossbar. see section ?27. port input/output? on page 171 for details on port i/o configuration. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 51 c8051f39x/37x 9.2.2. tracking modes the ad0tm bit in register adc0cn controls the adc0 track-and-hold mode. in its default state, the adc0 input is continuously tracked, except when a conversi on is in progress. when the ad0tm bit is logic 1, adc0 operates in low-power track-and-hold mode. in this mode, each conversion is preceded by a track- ing period of three sar clocks (after the start-of-con version signal). when the cnvstr signal is used to initiate conversions in low-power tracking mode, adc0 tracks only when cnvstr is low; conversion begins on the rising edge of cnvstr. see figure 9. 2 for track and convert timing details. tracking can also be disabled (shutdown) when the device is in low power standby or sleep modes. low-power track- and-hold mode is also useful when amux settings ar e frequently changed, due to the settling time require- ments described in section ?9.2.3. settling time requirements? on page 52. figure 9.2. 10-bit adc track and conversion example timing write '1' to ad0busy, timer 0, timer 2, timer 1, timer 3 overflow (ad0cm[2:0]=000, 001,010 011, 101) ad0tm=1 track convert low power mode ad0tm=0 track or convert convert track low power or convert sar clocks 123456789 1 0 1 1 1 2 123456789 sar clocks b. adc0 timing for internal trigger source 123456789 cnvstr (ad0cm[2:0]=100) ad0tm=1 a. adc0 timing for external trigger source sar clocks track or convert convert track ad0tm=0 track convert low power mode low power or convert 1 0 1 1 1 3 1 4 1 0 1 1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 52 preliminary rev. 0.71 9.2.3. settling time requirements a minimum tracking time is required before each conversi on to ensure that an accurate conversion is per- formed. this tracking time is determined by the am ux0 resistance, the adc0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. note that in low-power tracking mode, three sar clocks are used for tracking at the start of every conversion. for most applications, these three sar clocks will meet the mini mum tracking time requirements. figure 9.3 shows the equivalent adc0 input circuit. the required adc0 settling time for a given settling accuracy (sa) may be approximated by equation 9 .1. see table 7.10 for adc0 minimum settling time requirements as well as the mux impedance and sampling capacitor values. equation 9.1. adc0 settling time requirements where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the required settling time in seconds r total is the sum of the amux0 resistance and any external source resistance. n is the adc resolution in bits (10). figure 9.3. adc0 equivalent input circuits t 2 n sa ------ - ?? ?? r total c sample ? ln = r mux rc input = r mux * c sample r mux c sample c sample mux select mux select differential mode px.x px.x r mux c sample rc input = r mux * c sample mux select single-ended mode px.x www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 53 c8051f39x/37x sfr address = 0xbc; sfr page = all pages sfr definition 9.1. adc0cf : adc0 configuration bit76543210 name ad0sc[4:0] ad0ljst type r/w r/w r/w reset 11111000 bit name function 7:3 ad0sc[4:0] adc0 sar conversion clock period bits. sar conversion clock is derived fr om system clock by the fol- lowing equation, where ad0sc refers to the 5-bit value held in bits ad0sc4 ? 0. sar conversion clock requirements are given in the adc specification table 7.10. 2ad0ljst adc0 left justify select. 0: data in adc0h:adc0l re gisters are right-justified. 1: data in adc0h:adc0l re gisters are left-justified. 1:0 reserved must write 00b. ad0sc sysclk clk sar ------------- ---------- 1 ? = www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 54 preliminary rev. 0.71 sfr address = 0xbe; sfr page = all pages sfr address = 0xbd; sfr page = all pages sfr definition 9.2. adc0h: adc0 data word msb bit76543210 name adc0h[7:0] type r/w reset 00000000 bit name function 7:0 adc0h[7:0] adc0 data word high-order bits. for ad0ljst = 0: bits 7 ? 2 will read 000000b. bits 1 ? 0 are the upper 2 bits of the 10-bit adc0 data word. for ad0ljst = 1: bits 7 ? 0 are the most-significant bits of the 10-bit adc0 data word. sfr definition 9.3. adc0l: adc0 data word lsb bit76543210 name adc0l[7:0] type r/w reset 00000000 bit name function 7:0 adc0l[7:0] adc0 data word low-order bits. for ad0ljst = 0: bits 7 ? 0 are the lower 8 bits of the 10-bit data word. for ad0ljst = 1: bits 7 ? 6 are the lower 2 bits of the 10-bit data word. bits 5 ? 0 will read 000000b. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 55 c8051f39x/37x sfr address = 0xe8; sfr page = a ll pages; bit-addressable sfr definition 9.4. adc0cn: adc0 control bit76543210 name ad0en ad0tm ad0int ad0busy ad0wint ad0cm[2:0] type r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7ad0en adc0 enable bit. 0: adc0 disabled. adc0 is in low-power shutdown. 1: adc0 enabled. adc0 is active and ready for data conversions. 6ad0tm adc0 track mode bit. 0: normal track mode: when adc0 is ena bled, tracking is continuous unless a con- version is in progress. conversion begins immediately on start-of-conversion event, as defined by ad0cm[2:0]. 1: delayed track mode: when adc0 is enabled, input is tracked when a conversion is not in progress. a start-of-conversion si gnal initiates three sar clocks of additional tracking, and then begins the conversion. note that there is not a tracking delay when cnvstr is used (ad0cm[2:0] = 100). 5ad0int adc0 conversion comple te interrupt flag. 0: adc0 has not completed a data conv ersion since ad0int was last cleared. 1: adc0 has completed a data conversion. 4 ad0busy adc0 busy bit. 3ad0wint adc0 window compare interrupt flag. 0: adc0 window comparison data match ha s not occurred since this flag was last cleared. 1: adc0 window comparison data match has occurred. 2:0 ad0cm[2: 0] adc0 start of conversion mode select. 000: adc0 start-of-conversion s ource is write of 1 to ad0busy. 001: adc0 start-of-conversion source is overflow of timer 0. 010: adc0 start-of-conversion source is overflow of timer 2. 011: adc0 start-of-conversion source is overflow of timer 1. 100: adc0 start-of-conversion source is rising edge of external cnvstr. 101: adc0 start-of-conversion source is overflow of timer 3. 110: adc0 start-of-conversion source is overflow of timer 4. 111: adc0 start-of-conversion source is overflow of timer 5. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 56 preliminary rev. 0.71 9.3. programmable window detector the adc programmable window detector continuously compares the adc0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. this is especially effective in an interrupt-driven system, saving code space and cpu bandwidth while delivering faster system response times. the window detector interrupt flag (ad0wint in register adc0cn) can also be used in polled mode. the adc0 greater-than (adc0gth, adc0gtl) and less-than (adc0lth, adc0ltl) registers hold the comparison valu es. the window detector flag can be programmed to indicate when mea- sured data is inside or outside of the user-progr ammed limits, depending on the contents of the adc0 less-than and adc0 greater-than registers. sfr address = 0xc4; sfr page = all pages sfr address = 0xc3; sfr page = all pages sfr definition 9.5. adc0gth: adc 0 greater than data high byte bit76543210 name adc0gth[7:0] type r/w reset 11111111 bit name function 7:0 adc0gth[7:0] adc0 greater-than data wo rd high-order bits. sfr definition 9.6. adc0gtl: adc 0 greater-than data low byte bit76543210 name adc0gtl[7:0] type r/w reset 11111111 bit name function 7:0 adc0gtl[7:0] adc0 greater-than data word low-order bits. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 57 c8051f39x/37x sfr address = 0xc6; sfr page = all pages sfr address = 0xc5; sfr page = all pages sfr definition 9.7. adc0lth: adc0 less-than data high byte bit76543210 name adc0lth[7:0] type r/w reset 00000000 bit name function 7:0 adc0lth[7:0] adc0 less-than data word high-order bits. sfr definition 9.8. adc0ltl: a dc0 less-than data low byte bit76543210 name adc0ltl[7:0] type r/w reset 00000000 bit name function 7:0 adc0ltl[7:0] adc0 less-than data wo rd low-order bits. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 58 preliminary rev. 0.71 9.3.1. window detector example figure 9.4 shows two example window comparison s for right-justified, single-ended data, with adc0lth:adc0ltl = 0x0080 (128d) and adc0gth:adc0gtl = 0x0040 (64d). the input voltage can range from 0 to vref x (1023/1024) with respect to gnd, and is represented by a 10-bit unsigned integer value. in the left example, an ad0wint interrup t will be generated if th e adc0 conversion word (adc0h:adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0ltl (if 0x0040 < adc0h:adc0l < 0x0080). in the right exam ple, and ad0wint interr upt will be generated if the adc0 conversion word is outside of the range defined by the adc0gt and adc0lt registers (if adc0h:adc0l < 0x0040 or adc0h:adc0l > 0x0080). figure 9.5 shows an example using left-justi- fied data with the same comparison values. figure 9.4. adc window compare example: right-justified, single-ended data figure 9.5. adc window compare example: left-justified, single-ended data 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl adc0gth:adc0gtl www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 59 c8051f39x/37x 9.4. adc0 analog mu ltiplexer (c8051f390/2/4/6/ 8 and c8051f370/4 only) adc0 on the c8051f390/2/4/6/8 and c8051f370/4 has two analog multiplexers, re ferred to collectively as amux0. amux0 selects the positive and negative inputs to th e adc. any of the following may be selected as the positive input: port i/o pins, the on-chip temperature sensor, or the positive power supply (v dd ). any of the following may be selected as the negative input: port i/o pins, v ref , or gnd. when gnd is selected as the negative input, adc0 operates in single-ended mode; all other times, adc0 operates in differ- ential mode. the adc0 input channels are selected in the amx0p and amx0n registers as described in sfr definition 9.9 and sfr definition 9.10. figure 9.6. adc0 multiplexer block diagram important note about adc0 input configuration: port pins selected as adc0 inputs should be config- ured as analog inputs, and should be skipped by th e digital crossbar. to configure a port pin for analog input, set to ?0? the corresponding bit in register pnmdin. to force the cros sbar to skip a port pin, set to ?1? the corresponding bit in register pnskip. see section ?27. port input/output? on page 171 for more port i/ o configuration details. adc0 amux temp sensor amux vdd gnd p0.0 p2.3* amx0p amx0p4 amx0p3 amx0p2 amx0p1 amx0p0 amx0n amx0n4 amx0n3 amx0n2 amx0n1 amx0n0 ain+ ain- vref p0.0 p2.3* *p2.0-p2.3 only available as inputs on qfn24 packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 60 preliminary rev. 0.71 sfr address = 0xbb; sfr page = all pages sfr definition 9.9. amx0p: am ux0 positive channel select bit76543210 name amx0p[4:0] type rrr r/w reset 00011111 bit name function 7:5 unused read = 000b; write = don?t care. 4:0 amx0p[4:0] amux0 positive input selection. 00000: p0.0 00001: p0.1 00010: p0.2 00011: p0.3 00100: p0.4 00101: p0.5 00110: p0.6 00111: p0.7 01000: p1.0 01001: p1.1 01010: p1.2 01011: p1.3 01100: p1.4 01101: p1.5 01110: p1.6 01111: p1.7 10000: temp sensor 10001: v dd 10010: p2.0 (c8051f390/1/4/5 and c8051f37x only) 10011: p2.1 (c8051f390/1/4/5 and c8051f37x only) 10100: p2.2 (c8051f390/1/4/5 and c8051f37x only) 10101: p2.3 (c8051f390/1/4/5 and c8051f37x only) 10110 ? 11111: no input selected www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 61 c8051f39x/37x sfr address = 0xba; sfr page = all pages sfr definition 9.10. amx0n: am ux0 negative channel select bit76543210 name amx0n[4:0] type rrr r/w reset 00011111 bit name function 7:5 unused read = 000b; write = don?t care. 4:0 amx0n[4:0] amux0 negative input selection. 00000: p0.0 00001: p0.1 00010: p0.2 00011: p0.3 00100: p0.4 00101: p0.5 00110: p0.6 00111: p0.7 01000: p1.0 01001: p1.1 01010: p1.2 01011: p1.3 01100: p1.4 01101: p1.5 01110: p1.6 01111: p1.7 10000: v ref 10001: gnd (adc in single-ended mode) 10010: p2.0 (c8051f390/1/4/5 and c8051f37x only) 10011: p2.1 (c8051f390/1/4/5 and c8051f37x only) 10100: p2.2 (c8051f390/1/4/5 and c8051f37x only) 10101: p2.3 (c8051f390/1/4/5 and c8051f37x only) 10110 ? 11111: no input selected www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 62 preliminary rev. 0.71 10. temperature sensor (c8051f390 /2/4/6/8 and c8051f370/4 only) a fully c8051f33x-compatible temperature sensor is included on the c8051f390/2/4/6/8 and c8051f370/ 4 and accessed via the adc multiplexer in single-en ded configuration. for the self-contained precision temperature sensor, refer to section 8. to use the adc to measure the temperature sensor, the adc mux channel should be configured to con- nect to the temperature sensor. the temperature sensor transfer function is shown in figure 10.1. the out- put voltage (v temp ) is the positive adc input when the adc mult iplexer is set correctly. the tempe bit in register ref0cn enables/disables the temperature sens or, as described in sfr definition 12.1. while dis- abled, the temperature sensor defaults to a high impedance state and any adc measurements performed on the sensor will result in meaningle ss data. refer to table 7.11 for the slope and offset parameters of the temperature sensor. figure 10.1. temperature sensor transfer function temperature voltage v temp = ( slope x temp c ) + offset offset (v at 0 celsius) slope (v / deg c) temp c = (v temp - offset ) / slope www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 63 c8051f39x/37x 10.1. calibration the uncalibrated temperature sensor output is extrem ely linear and suitable for relative temperature mea- surements (see table 7.11 on page 39 for specificati ons). for absolute temperature measurements, offset and/or gain calibration is recommended. figure 10.2 shows the typical te mperature sensor error assuming a 1-point calibration at 0 c. parame- ters that affect adc meas urement, in particular the voltage refe rence value, will also affect temper- ature measurement. figure 10.2. temperature sensor error with 1-point calibration at 0 c -40.00 -20.00 0.00 20.00 40.00 60.00 80.00 temperature (degrees c) error (degrees c) -5.00 -4.00 -3.00 -2.00 -1.00 0.00 1.00 2.00 3.00 4.00 5.00 -5.00 -4.00 -3.00 -2.00 -1.00 0.00 1.00 2.00 3.00 4.00 5.00 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 64 preliminary rev. 0.71 11. 10-bit current mode dacs (i da0, ida1, c8051f390/2/4/6/8 and c8051f370/4 only) the c8051f390/2/4/6/8 and c8051f370/4 devices incl ude two 10-bit current-mode digital-to-analog con- verters (idacs). the maximum current output of the idacs can be adjusted for three different current set- tings; 0.5 ma, 1 ma, and 2 ma. the idacs are enable d or disabled with the idanen bit in the control register for that idac (see sfr definition 11.1 and sfr definition 11.4). when idanen is set to 0, the idac output behaves as a normal gpio pin. when idanen is set to 1, the digital output drivers and weak pullup for the idac pin are automatically disabled, and the pin is connected to the idac output. an internal bandgap bias generator is used to generate a referenc e current for the idac whenever it is enabled. when using an idac, the crossbar skip functionality should be enabled on the idac output pin, to force the crossbar to skip the output pin. 11.1. idac output scheduling the idacs feature a flexible outpu t update mechanism which allows for seamless full-scale changes and supports jitter-free updates for waveform generati on. three update modes are provided, allowing idac output updates on a write to idanh, on a timer overflow, or on an external pin edge. 11.1.1. update output on-demand in its default mode (idancn.[6:4] = 111) the idac outp ut is updated ?on-demand? on a write to the high- byte of the idac data register (idanh). it is important to note that writes to idanl are held in this mode, and have no effect on the idac output until a write to idanh takes place. if writing a full 10-bit word to the idac data registers, the 10-bit data word is written to the low byte (idanl) and high byte (idanh) data reg- isters. data is latched into the idac after a write to the idanh register, so the write sequence should be idanl followed by idanh if the full 10-bit resolution is required. the idac can be used in 8-bit mode by initializing idanl to the desired value (typically 0x00), and writing data to only idanh (see section 11.3 for information on the format of the 10-bit idac data word within the 16-bit sfr space). figure 11.1. ida0 functional block diagram ida0 10 ida0 ida0cn ida0en ida0cm2 ida0cm1 ida0cm0 ida0omd1 ida0omd0 ida0h ida0l latch 8 2 ida0h timer 0 timer 1 timer 2 timer 3 cnvstr www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 65 c8051f39x/37x figure 11.2. ida1 functional block diagram ida1 10 ida1 ida1cn ida1en ida1cm2 ida1cm1 ida1cm0 ida1omd1 ida1omd0 ida1h ida1l latch 8 2 ida1h timer 0 timer 5 timer 2 timer 3 cnvstr www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 66 preliminary rev. 0.71 11.1.2. update output based on timer overflow the idac outputs can use a timer overflow to schedule an output update event. this feature is useful in systems where the idac is used to generate a waveform of a defined sampling rate by eliminating the effects of variable interrupt latency and instruction execution on the timing of the idac output. when the idancm bits (idancn.[6:4]) are set to 000, 001, 010 or 011, writes to both idac data registers (idanl and idanh) are held until an associated timer overflow event occurs, at which time the idanh:idanl contents are copied to the idac input latches, allowing the idac output to change to the new value. 11.1.3. update output based on cnvstr edge the idac output can also be configured to update on a rising edge, falling edge, or both edges of the external cnvstr signal. when the idan cm bits (idancn.[6:4]) are set to 100, 101, or 110, writes to both idac data registers (idanl and idanh) are held unt il an edge occurs on the cnvstr input pin. the par- ticular setting of the idancm bits determines whethe r idac outputs are updated on rising, falling, or both edges of cnvstr. when a corresponding edge occurs , the idanh:idanl contents are copied to the idac input latches, allowing the idac output to change to the new value. 11.2. idac reset behavior by default, both idac modules revert to a disabled st ate on any reset source. it is possible to keep the idac outputs enabled through all but a por or vdd m onitor reset, however. when the idanrp bit in the idancn register is set to 1, any reset other than a por or vdd monito r reset will not affect the idac out- put. the idac output will remain enabled and the value in the idac output word is maintained. 11.3. idac output mapping the idac data registers (idanh and idanl) are left -justified, meaning that the eight msbs of the idac output word are mapped to bits 7 ? 0 of the idanh register, and the two lsbs of the idac output word are mapped to bits 7 and 6 of the idanl register. the data word mapping for the idacs is shown in figure 11.3. figure 11.3. ida0 data word mapping the full-scale output current of t he idac is selected using the idanom d bits (idancn[1:0]). by default, the idac is set to a full-scale output current of 2 m a. the idanomd bits can also be configured to provide full-scale output currents of 1 ma or 0.5 ma, as show n in sfr definition 11.1 and sfr definition 11.4. idanh idanl b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 input data word (idan9?idan0) output current idanomd[1:0] = 1x output current idanomd[1:0] = 01 output current idanomd[1:0] = 00 0x000 0 ma 0 ma 0 ma 0x001 1/1024 x 2 ma 1/1024 x 1 ma 1/1024 x 0.5 ma 0x200 512/1024 x 2 ma 512/1024 x 1 ma 512/1024 x 0.5 ma 0x3ff 1023/1024 x 2 ma 1023/1024 x 1 ma 1023/1024 x 0.5 ma www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 67 c8051f39x/37x sfr address = 0xb9; sfr page = 0 sfr definition 11.1. ida0cn: ida0 control bit76543210 name ida0en ida0cm[2:0] i da0rp ida0omd[1:0] type r/w r/w r r/w r/w reset 01110varies10 bit name function 7ida0en ida0 enable. 0: ida0 disabled. 1: ida0 enabled. 6:4 ida0cm[2:0] ida0 update source select bits. 000: dac output updates on timer 0 overflow. 001: dac output updates on timer 1 overflow. 010: dac output updates on timer 2 overflow. 011: dac output updates on timer 3 overflow. 100: dac output updates on rising edge of cnvstr. 101: dac output updates on falling edge of cnvstr. 110: dac output updates on any edge of cnvstr. 111: dac output updates on write to ida0h. 3 reserved write = 0b. 2ida0rp ida0 reset persistence. 0: ida0 is disabled by any reset source. 1: ida0 will remain enabled through any reset source except a power-on-reset. this bit is reset to 0 by a power on reset, but is sticky through all other reset sources. when setting ida0rp to 1, ida0en must be set to 1 also in the same mov instruction. 1:0 ida0omd[1:0] ida0 output mode select bits. 00: 0.5 ma full-scale output current. 01: 1.0 ma full-scale output current. 1x: 2.0 ma full-scale output current. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 68 preliminary rev. 0.71 sfr address = 0x97; sfr page = 0 sfr address = 0x96; sfr page = 0 sfr definition 11.2. ida0h: ida0 data word msb bit76543210 name ida0[9:2] type r/w reset 00000000 bit name function 7:0 ida0[9:2] ida0 data word high-order bits. upper 8 bits of the 10-bit ida0 data word. sfr definition 11.3. ida0l: ida0 data word lsb bit76543210 name ida0[1:0] type r/w rrrrrr reset 00000000 bit name function 7:6 ida0[1:0] ida0 data word low-order bits. lower 2 bits of the 10-bit ida0 data word. 5:0 unused unused. read = 000000b. write = don?t care. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 69 c8051f39x/37x sfr address = 0xb9; sfr page = f sfr definition 11.4. ida1cn: ida1 control bit76543210 name ida1en ida1cm[2:0] i da1rp ida1omd[1:0] type r/w r/w r r/w r/w reset 01110varies10 bit name function 7ida1en ida1 enable. 0: ida1 disabled. 1: ida1 enabled. 6:4 ida1cm[2:0] ida0 update source select bits. 000: dac output updates on timer 0 overflow. 001: dac output updates on timer 5 overflow. 010: dac output updates on timer 2 overflow. 011: dac output updates on timer 3 overflow. 100: dac output updates on rising edge of cnvstr. 101: dac output updates on falling edge of cnvstr. 110: dac output updates on any edge of cnvstr. 111: dac output updates on write to ida1h. 3 reserved write = 0b. 2ida1rp ida1 reset persistence. 0: ida1 is disabled by any reset source. 1: ida1 will remain enabled through any reset source except a power-on-reset. this bit is reset to 0 by a power on reset, but is sticky through all other reset sources. when setting ida1rp to 1, ida1en must be set to 1 also in the same move instruction. 1:0 ida1omd[1:0] ida1 output mode select bits. 00: 0.5 ma full-scale output current. 01: 1.0 ma full-scale output current. 1x: 2.0 ma full-scale output current. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 70 preliminary rev. 0.71 sfr address = 0x97; sfr page = f sfr address = 0x96; sfr page = f sfr definition 11.5. ida1h: ida1 data word msb bit76543210 name ida1[9:2] type r/w reset 00000000 bit name function 7:0 ida1[9:2] ida1 data word high-order bits. upper 8 bits of the 10-bit ida1 data word. sfr definition 11.6. ida1l: ida1 data word lsb bit76543210 name ida1[1:0] type r/w rrrrrr reset 00000000 bit name function 7:6 ida1[1:0] ida1 data word low-order bits. lower 2 bits of the 10-bit ida1 data word. 5:0 unused unused. read = 000000b. write = don?t care. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 71 c8051f39x/37x 12. voltage reference options the voltage reference multiplexer for the adc is configurable to use an externally connected voltage refer- ence, the on-chip reference voltage generator routed to the vref pin, the unregulated power supply volt- age (v dd ), or the regulated 1.8 v internal supply (see figure 12.1). the refsl bit in the reference control register (ref 0cn, sfr definition 12.1) selects the reference source for the adc. for an external source or the on-chip reference, refsl should be set to 0 to select the vref pin. to use v dd as the ref- erence source, refsl should be set to 1. to override this selection and use the internal regulator as the reference source, the rego vr bit can be set to 1. the biase bit enables the inte rnal voltage bias ge nerator, which is used by ma ny of the analo g peripherals on the device. this bias is automatically enabled when any peripheral which requir es it is enabled, and it does not need to be enabled manually. the bias generator may be enabled manually by writing a 1 to the biase bit in register ref0cn. the el ectrical specifications for the vo ltage reference circuit are given in table 7.13. the c8051f390/2/4/6/8 and c8051f370/4 devices also include an on-chip voltage reference circuit which consists of a 1.2 v, temperature stable bandgap voltage reference generator and a selectable-gain output buffer amplifier. the buffer is configured for 1x or 2x gain using the refbgs bit in register ref0cn. on the 1x gain setting the output voltage is nominally 1.2 v, and on the 2x gain setting the output voltage is nominally 2.4 v. the on-chip voltage reference can be driven on the vref pin by setting the refbe bit in register ref0cn to a 1. the maximum load seen by the vref pin must be less than 200 a to gnd. bypass capacitors of 0.1 f and 4.7 f are recomme nded from the vref pin to gnd, and a minimum of 0.1uf is required. if the on-chip reference is not used, the refbe bit should be cleared to 0. electrical specifications for the on-chip voltage reference are given in table 7.13. important note about the vref pin: when using either an external vo ltage reference or the on-chip ref- erence circuitry, the vref pin should be configured as an analog pin and skipped by the digital crossbar. refer to section ?27. port input/output? on page 171 for the location of the vref pin, as well as details of how to configure the pin in analog mode and to be skipped by the crossbar. figure 12.1. voltage reference functional block diagram to analog mux vdd vref r1 vdd external voltage reference circuit gnd temp sensor en bias generator to adc, idac, internal oscillators, reference, tempsensor en ioscen 0 1 ref0cn refsl tempe biase refbe regovr refbgs refbe recommended bypass capacitors + 4.7 ? f0.1 ? f vref (to adc) 0 1 internal regulator regovr 1.2v reference en 1x/2x refbgs www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 72 preliminary rev. 0.71 sfr address = 0xd1; sfr page = all pages sfr definition 12.1. ref0 cn: reference control bit76543210 name refbgs regovr refsl tempe biase refbe type r/w r r r/w r/w r/w r/w r/w reset 00000000 bit name function 7 refbgs reference buffer gain select. this bit selects between 1x and 2x gain for the on-chip voltage ref- erence buffer. 0: 2x gain 1: 1x gain 6:5 unused read = 00b; write = don?t care. 4regovr regulator refere nce override. this bit ?overrides? the refsl bit, and allows the internal regulator to be used as a reference source. 0: the voltage reference source is selected by the refsl bit. 1: the internal regulator is used as the voltage reference. 3refsl voltage reference select. this bit selects the ad cs voltage reference. 0: v ref pin used as voltage reference. 1: v dd used as voltage reference. 2tempe temperature sensor enable bit. 0: internal temperature sensor off. 1: internal temperature sensor on. 1 biase internal analog bias generator enable bit. 0: internal bias generator off. 1: internal bias generator on. 0 refbe on-chip reference buffer enable bit. 0: on-chip reference buffer off. 1: on-chip reference buffer on. internal voltage reference driven on the v ref pin. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 73 c8051f39x/37x 13. voltage regulator c8051f39x/37x devices include an internal regulator that regulates the internal core supply from a v dd supply of 1.8 to 3.6 v. the regulator has two power-saving modes built in to help reduce current consump- tion in low-power applications. these modes are accessed through the reg0cn register. 13.1. power modes under default conditio ns, the internal regulator will remain on when the device enters stop mode. this allows any enabled reset source to generate a reset for the device and bring the device out of stop mode. for additional power savings, the stopcf bit can be used to shut down the regulator and the internal power network of the device when the part enters stop mode. when stopcf is set to 1, the rst pin and a full power cycle of the device are the only methods of generating a reset. sfr address = 0xc9; sfr page = all pages sfr definition 13.1. reg0cn: voltage regulator control bit76543210 name stopcf type r/w r/w r/w reset 00000000 bit name function 7:4 reserved must write 0000b. 3stopcf stop mode configuration. this bit configures the regulator?s behavior when the device enters stop mode. 0: regulator is still active in stop mode. any enabled reset source will reset the device. 1: regulator is shut down in stop mode. only the rst pin or power cycle can reset the device. 2:0 reserved must write 000b. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 74 preliminary rev. 0.71 14. comparator0 c8051f39x/37x devices include an on-chip programmable voltage comparator, comparator0, shown in figure 14.1. the comparator offers programmable response time a nd hysteresis, an analog in put multiplexer, and two outputs that are optionally availabl e at the port pins: a synchronous ?latched? output (cp0), or an asyn- chronous ?raw? output (cp0a). the asynchronous cp0a signal is available even when the system clock is not active. this allows the comparator to operate and generate an output with the device in stop mode. when assigned to a port pin, the comparator outpu t may be configured as open drain or push-pull (see section ?27.4. port i/o initialization? on page 178). comparator0 may also be used as a reset source (see section ?24.5. comparator 0 reset? on page 157), or as a tr igger to kill a pca output channel. the comparator0 inputs are selected by the comparator input multiplexer, as detailed in section ?14.1. comparator multiplexer? on page 78. figure 14.1. comparator0 functional block diagram the comparator output can be polled in software, used as an interrupt source, and/or routed to a port pin. when routed to a port pin, the co mparator output is available asyn chronous or synchronous to the system clock; the asynchronous output is available even in stop mode (with no system clock active). when dis- abled, the comparator output (if assigned to a port i/o pin via the crossbar) defaults to the logic low state, and the power supply to the compar ator is turned off. see section ?27.3. priority crossbar decoder? on page 176 for details on configuring comparator outputs via the digital crossbar. comparator inputs can be externally driven from ?0.25 v to (v dd ) + 0.25 v without damage or upset. the complete comparator elec- trical specifications are given in section ?7. electrical characteristics? on page 32. vdd reset decision tree + - crossbar q q set clr d q q set clr d (synchronizer) gnd cp0 + cp0 - cpt0md cp0rie cp0fie cp0md1 cp0md0 cp0 cp0a cp0 interrupt 0 1 0 1 cp0rif cp0fif 0 1 cp0en 0 1 ea comparator input mux cpt0cn cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 75 c8051f39x/37x the comparator response time may be configured in software via the cpt0md register (see sfr defini- tion 14.2). selecting a longer response time reduces the comparator supply current. figure 14.2. comparator hysteresis plot the comparator hysteresis is software-programmabl e via its comparator cont rol register cpt0cn. the user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hyst eresis around the threshold voltage. the comparator hysteresis is programmed using bits3 ? 0 in the comparator control register cpt0cn (shown in sfr definition 14.1). the amount of negative hysteresis voltage is determined by the settings of the cp0hyn bits. as shown in figure 14.2, settings of 20, 10, or 5 mv of negative hysteresis can be pro- grammed, or negative hysteresis can be disabled. in a similar way, the amount of positive hysteresis is determined by the setting the cp0hyp bits. comparator interrupts can be genera ted on both rising-e dge and falling-edge output transitions. (for inter- rupt enable and priority control, see section ?20.1. mcu interrupt sour ces and vectors? on page 116). the cp0fif flag is set to logic 1 upon a comparator falling-edge occurrence, and the cp0rif flag is set to logic 1 upon the comparator rising-edge occurrence. once set, these bits remain set until cleared by soft- ware. the comparator rising-edge interrupt mask is enabled by setting cp0rie to a logic 1. the comparator0 falling-edge interrupt mask is enabled by setting cp0fie to a logic 1. the output state of the comparator can be obtained at any time by reading the cp0out bit. the compar- ator is enabled by setting the cp0en bit to logic 1, and is disabled by clearing this bit to logic 0. note that false rising ed ges and falling edges can be detected when the comparator is first powered on or if changes are made to the hy steresis or response time control bits. therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is enabled or its mode bits have been changed. positive hysteresis voltage (programmed with cp0hyp bits) negative hysteresis voltage (programmed by cp0hyn bits) vin- vin+ inputs circuit configuration + _ cp0+ cp0- cp0 vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 76 preliminary rev. 0.71 sfr address = 0x9b; sfr page = all pages sfr definition 14.1. cpt0 cn: comparator0 control bit76543210 name cp0en cp0out cp0rif cp0fif cp0hyp[1:0] cp0hyn[1:0] type r/w r r/w r/w r/w r/w reset 00000000 bit name function 7 cp0en comparator0 enable bit. 0: comparator0 disabled. 1: comparator0 enabled. 6cp0out comparator0 output state flag. 0: voltage on cp0+ < cp0 ? . 1: voltage on cp0+ > cp0 ? . 5cp0rif comparator0 rising-edge flag. must be cleared by software. 0: no comparator0 rising edge has occurred since this flag was last cleared. 1: comparator0 rising edge has occurred. 4cp0fif comparator0 falling-edge flag. must be cleared by software. 0: no comparator0 falling-edge ha s occurred since this flag was last cleared. 1: comparator0 fallin g-edge has occurred. 3:2 cp0hyp[1:0] comparator0 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. 1:0 cp0hyn[1:0] comparator0 negative hysteresis control bits. 00: negative hyst eresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 77 c8051f39x/37x sfr address = 0x9d; sfr page = all pages sfr definition 14.2. cpt0md: comparator0 mode selection bit76543210 name cp0rie cp0fie cp0md[1:0] type rrr/wr/wrr r/w reset 00000010 bit name function 7:6 unused unused. read = 00b, write = don?t care. 5cp0rie comparator0 rising-edge interrupt enable. 0: comparator0 rising-edge interrupt disabled. 1: comparator0 rising-edge interrupt enabled. 4cp0fie comparator0 falling-edge interrupt enable. 0: comparator0 falling-ed ge interrupt disabled. 1: comparator0 falling-ed ge interrupt enabled. 3:2 unused unused. read = 00b, write = don?t care. 1:0 cp0md[1:0] comparator0 mode select. these bits affect the response time and power consumption for comparator0. 00: mode 0 (fastest response time, highest power con- sumption) 01: mode 1 10: mode 2 11: mode 3 (slowest response time, lowest power con- sumption) www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 78 preliminary rev. 0.71 14.1. comparator multiplexer c8051f39x/37x devices include an analog input multip lexer to connect port i/o pins to the comparator inputs. the comparator0 inputs are selected in the cpt0mx register (sfr definition 14.3). the cmx0p1 ? cmx0p0 bits select the comparator0 positive input; the cmx0n1 ? cmx0n0 bits select the comparator0 negative input. important note about comparator inputs: the port pins selected as comparator inputs should be configured as analog inputs in their associ ated port configuration register, and configured to be skipped by the crossbar (for details on port configur ation, see section ?27.6. special function registers for accessing and configuring port i/o? on page 183). figure 14.3. comparator input multiplexer block diagram + - cp0 + p0.0 cp0 - cpt0mx cmx0n3 cmx0n2 cmx0n1 cmx0n0 cmx0p3 cmx0p2 cmx0p1 cmx0p0 p0.2 p0.4 p0.6 p1.0 p1.2 p1.4 p1.6 p2.0* p2.2* p0.1 p0.3 p0.5 p0.7 p1.1 p1.3 p1.5 p1.7 p2.1* p2.3* gnd vdd *p2.0-p2.3 only available as inputs on qfn24 packaging www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 79 c8051f39x/37x sfr address = 0x9f; sfr page = all pages sfr definition 14.3. cpt0mx: comparator0 mux selection bit76543210 name cmx0n[3:0] cmx0p[3:0] type r/w r/w reset 11111111 bit name function 7:4 cmx0n[3:0] comparator0 negative input mux selection. 0000: p0.1 0001: p0.3 0010: p0.5 0011: p0.7 0100: p1.1 0101: p1.3 0110: p1.5 0111: p1.7 1000: p2.1 (c8051f390/1/4/5 and c8051f37x only) 1001: p2.3 (c8051f390/1/4/5 and c8051f37x only) 1010-1111: none 3:0 cmx0p[3:0] comparator0 positive input mux selection. 0000: p0.0 0001: p0.2 0010: p0.4 0011: p0.6 0100: p1.0 0101: p1.2 0110: p1.4 0111: p1.6 1000: p2.0 (c8051f390/1/4/5 and c8051f37x only) 1001: p2.2 (c8051f390/1/4/5 and c8051f37x only) 1010-1111: none www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 80 preliminary rev. 0.71 15. cip-51 microcontroller the mcu system controller core is the cip-51 microcon troller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemble rs and compilers can be used to develop soft- ware. the mcu family has a superset of all the peri pherals included with a standard 8051. the cip-51 also includes on-chip debug hardware (see descriptio n in section 33), and interfaces directly with the ana- log and digital subsystems providing a complete data acqu isition or control-system so lution in a single inte- grated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (s ee figure 15.1 for a block diagram). the cip-51 includes the following features: performance the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan- dard 8051 architecture. in a standar d 8051, all instructions except fo r mul and div take 12 or 24 system clock cycles to execute, and usually have a maximu m system clock of 12 mhz. by contrast, the cip-51 core executes 70% of its instructions in one or tw o system clock cycles, with no instructions taking more than eight system clock cycles. figure 15.1. cip-51 block diagram ? fully compatible with mc s-51 instruction set ? 50 mips peak throughput with 49 mhz clock ? 0 to 49 mhz clock frequency ? extended interrupt handler ? reset input ? power management modes ? on-chip debug logic ? program and data memory security data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram d8 stack pointer d8 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 81 c8051f39x/37x with the cip-51's maximum system clock at 48 mhz, it has a peak throughput of 48 mips. the cip-51 has a total of 109 instructions. the table below shows the to tal number of instructions that require each execu- tion time. programming and debugging support in-system programming of the eprom program memory and communication with on-chip debug support logic is accomplished via the silicon l abs 2-wire development interface (c2). the on-chip debug support logic facilitates full speed in-circuit debugging, a llowing the setting of hardware breakpoints, starting, stopping and single stepping th rough program execution (including interrupt service routines), examination of the program's call stack, a nd reading/writing the conten ts of registers and mem- ory. this method of on-chip debugging is completely non-intrusive, requiring no ram, stack, timers, or other on-chip resources. c2 details can be found in section ?33. c2 interface? on page 295. the cip-51 is support ed by development tools from silicon labs and third party vendors. silicon labs pro- vides an integrated development environment (ide) in cluding editor, debugger and programmer. the ide's debugger and programmer interface to the cip-51 via the c2 interface to provide fast and efficient in-sys- tem device programming and debugging. third party macro assemblers and c compilers are also avail- able. 15.1. instruction set the instruction set of the cip-51 system controller is fully compatible with the standard mcs-51? instruc- tion set. standard 8051 development tools can be used to develop software for the cip-51. all cip-51 instructions are the binary and fu nctional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, in struction timing is different than that of the stan- dard 8051. 15.1.1. instruction and cpu timing in many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instruction ti mings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instruct ions take one less clock cycle to complete when the branch is not taken as o pposed to when the branch is taken. table 15.1 is the cip-51 instruction set summary, which includes the mnemonic, number of byte s, and number of clock cycles for each instruction. clocks to execute 1 2 2/4 3 3/5 4 5 4/6 6 8 number of instructions 2650510752121 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 82 preliminary rev. 0.71 table 15.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract imme diate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 83 c8051f39x/37x xrl direct, #data exclusive-or immediate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 table 15.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 84 preliminary rev. 0.71 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/4 jnc rel jump if carry is not set 2 2/4 jb bit, rel jump if direct bit is set 3 3/5 jnb bit, rel jump if direct bit is not set 3 3/5 jbc bit, rel jump if direct bit is set and clear bit 3 3/5 program branching acall addr11 absolute subroutine call 2 4* lcall addr16 long subroutine call 3 5* ret return from subroutine 1 6* reti return from interrupt 1 6* ajmp addr11 absolute jump 2 4* ljmp addr16 long jump 3 5* sjmp rel short jump (relative address) 2 4* jmp @a+dptr jump indirect relative to dptr 1 4* jz rel jump if a equals zero 2 2/4* jnz rel jump if a does not equal zero 2 2/4* cjne a, direct, rel compare direct byte to a and jump if not equal 3 4/6* cjne a, #data, rel compare immediate to a and jump if not equal 3 3/5* cjne rn, #data, rel compare immediate to register and jump if not equal 33/5* cjne @ri, #data, rel compare immediate to indirect and jump if not equal 34/6* djnz rn, rel decrement register and jump if not zero 2 2/4* djnz direct, rel decrement direct byte and jump if not zero 3 3/5* nop no operation 1 1 * clock cycles for branch in structions with prefetch enabled, align = 0, flrt = 0 table 15.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 85 c8051f39x/37x 15.2. cip-51 re gister descriptions following are descriptions of sfrs related to the opera tion of the cip-51 system controller. reserved bits should always be written to the value indicated in the sfr description. future product versions may use these bits to implem ent new features in which ca se the reset value of the bi t will be the indicated value, selecting the feature's default state. detailed descriptions of the remaining sfrs are included in the sec- tions of the datasheet associated with their corresponding system function. notes on registers, operands and addressing modes: rn - register r0?r7 of the curr ently selected register bank. @ri - data ram location addressed indirectly through r0 or r1. rel - 8-bit, signed (two?s complement) offset relative to the first byte of the following instruction. used by sjmp and all conditional jumps. direct - 8-bit internal data location?s address. this could be a direct-access data ram location (0x00? 0x7f) or an sfr (0x80?0xff). #data - 8-bit constant #data16 - 16-bit constant bit - direct-accessed bit in data ram or sfr addr11 - 11-bit destination address used by acall and ajmp. the destination mu st be within the same 2 kb page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by lcall a nd ljmp. the destination may be anywhere within the 8 kb program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 86 preliminary rev. 0.71 sfr address = 0x82; sfr page = all pages sfr address = 0x83; sfr page = all pages sfr definition 15.1. dpl: data pointer low byte bit76543210 name dpl[7:0] type r/w reset 00000000 bit name function 7:0 dpl[7:0] data pointer low. the dpl register is the low byte of the 16-bit dptr. sfr definition 15.2. dph: data pointer high byte bit76543210 name dph[7:0] type r/w reset 00000000 bit name function 7:0 dph[7:0] data pointer high. the dph register is the high byte of the 16-bit dptr. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 87 c8051f39x/37x sfr address = 0x81; sfr page = all pages sfr address = 0xe0; sfr page = a ll pages; bit-addressable sfr definition 15.3. sp: stack pointer bit76543210 name sp[7:0] type r/w reset 00000111 bit name function 7:0 sp[7:0] stack pointer. the stack pointer holds the location of the top of the stack. the stack pointer is incremented before every push operation. the sp register defaults to 0x07 after reset. sfr definition 15.4. acc: accumulator bit76543210 name acc[7:0] type r/w reset 00000000 bit name function 7:0 acc[7:0] accumulator. this register is the accumulator for arithmetic operations. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 88 preliminary rev. 0.71 sfr address = 0xf0; sfr page = all pages; bit-addressable sfr definition 15.5. b: b register bit76543210 name b[7:0] type r/w reset 00000000 bit name function 7:0 b[7:0] b register. this register serves as a seco nd accumulator for certain arith- metic operations. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 89 c8051f39x/37x sfr address = 0xd0; sfr page = a ll pages; bit-addressable sfr definition 15.6. psw: program status word bit76543210 name cy ac f0 rs[1:0] ov f1 parity type r/w r/w r/w r/w r/w r/w r reset 00000000 bit name function 7cy carry flag. this bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). it is cleared to logic 0 by all other arithmetic operations. 6ac auxiliary carry flag. this bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to logic 0 by all other arithmetic operations. 5f0 user flag 0. this is a bit-addressable, general purpose flag for use under soft- ware control. 4:3 rs[1:0] register bank select. these bits select which register bank is used during register accesses. 00: bank 0, addresses 0x00-0x07 01: bank 1, addresses 0x08-0x0f 10: bank 2, addresses 0x10-0x17 11: bank 3, addresses 0x18-0x1f 2ov overflow flag. this bit is set to 1 under the following circumstances: ?? an add, addc, or subb instruction causes a sign-change overflow. ?? a mul instruction results in an overflow (result is greater than 255). ?? a div instruction causes a divide-by-zero condition. the ov bit is cleared to 0 by the add, addc, subb, mul, and div instructions in all other cases. 1f1 user flag 1. this is a bit-addressable, general purpose flag for use under soft- ware control. 0parity parity flag. this bit is set to logic 1 if the su m of the eight bits in the accumula- tor is odd and cleared if the sum is even. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 90 preliminary rev. 0.71 16. prefetch engine the c8051f39x/37x family of devices incorporate a 2- byte prefetch engine. because the access time of the flash memory is 40 ns, and the minimum instruction time is roughly 20 ns, the prefetch engine is nec- essary for full-speed code execution. instructions are read from flash memory two bytes at a time by the prefetch engine and given to the cip-51 processor core to execute. when running linear code (code with- out any jumps or branches), the prefetch engine allows instructions to be executed at full speed. when a code branch occurs, the proc essor may be stalled for up to two cl ock cycles while the next set of code bytes is retrieved from flash memory. note: the prefetch engine should be disabled when the device is in suspend mode to save power. sfr address = 0xb5; sfr page = all pages sfr definition 16.1. pfe0cn: prefetch engine control bit76543210 name pfen type rrr/wrrrrr reset 00100000 bit name function 7:6 unused unused. read = 00b, write = don?t care. 5pfen prefetch enable. this bit enables the prefetch engine. 0: prefetch engine is disabled. 1: prefetch engine is enabled. 4:0 unused unused. read = 00000b. write = don?t care. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 91 c8051f39x/37x 17. memory organization the memory organization of the cip-51 system controller is similar to that of a standard 8051. there are two separate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different instruction types. the memory organization of the c8051f39x/37x device family is shown in figure 17.1. not shown in figure 17.1 is 512 bytes of byte- addressable eeprom available on c8051f37x, accessible by smbus/i 2 c (see section 22). figure 17.1. c8051f39x/37x memory map f always reads 0x00 program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 768 bytes (accessable using movx instruction) 0x0000 0x02ff same 1024 bytes as from 0x0000 to 0x03ff, wrapped on 1024-byte boundaries 0x0300 0xffff 0x03ff 0x0400 16 kb flash (in-system programmable in 512 byte sectors) c8051f390/1/2/3, c8051f370/1/4/5 0x0000 0x4000 8 kb flash (in-system programmable in 512 byte sectors) c8051f394/5/6/7 0x0000 0x2000 4 kb flash (in-system programmable in 512 byte sectors) c8051f398/9 0x0000 0x1000 0 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 92 preliminary rev. 0.71 17.1. program memory the cip-51 core has a 64 kb program memory space. the c8051f39x/37x implements 16 kb of this pro- gram memory space as in-system, re-programmable flash memory, organized in a contiguous block from addresses 0x0000 to 0x3fff. the address 0x3fff serves as the security lock byte for the device, and addresses above 0x3fff are reserved. figure 17.2. flash program memory map 17.1.1. movx instructio n and program memory the movx instruction in an 8051 device is typica lly used to access external data memory. on the c8051f39x/37x devices, the movx instruction is norma lly used to read and write on-chip xram, but can be re-configured to write and erase on-chip flash me mory space. movc instructions are always used to read flash memory, while movx write instructions are used to erase an d write flash. this flash access feature provides a mechanism for the c8051f39x/37x to update program code and use the program mem- ory space for non-volatile data storage. refer to section ?21. flash memory? on page 129 for further details. 17.2. data memory the c8051f39x/37x device family includes 1024 byte s of ram data memory. 256 bytes of this memory is mapped into the internal ram space of the 8051. 768 bytes of this memory is on-chip ?external? memory. the data memory map is shown in figure 17.1 for reference. 17.2.1. internal ram there are 256 bytes of internal ram mapped into the data memory space from 0x00 through 0xff. the lower 128 bytes of data memory are used for genera l purpose registers and scratch pad memory. either direct or indirect addressing may be used to access the lower 128 bytes of data memory. locations 0x00 through 0x1f are addressable as four banks of gene ral purpose registers, each bank consisting of eight byte-wide registers. the next 16 bytes, locations 0x 20 through 0x2f, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by indirect addressing. this region occupies the same address space as the special function regist ers (sfr) but is physically separate from the sfr space. the addressing mode used by an instructio n when accessing locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data memory space or the sfrs. instructions that use direct addressing will access the sfr space. instructions using indirect addressing above 0x7f access the lock byte 0x0000 0x0fff 0x0ffe flash memory organized in 512-byte pages 0x0e00 lock byte page flash memory space lock byte 0x0000 0x1fff 0x1ffe 0x1e00 lock byte page flash memory space lock byte 0x0000 0x3fff 0x3ffe 0x3e00 lock byte page flash memory space c8051f390/1/2/3 c8051f370/1/4/5 c8051f392/3/6/7 c8051f398/9 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 93 c8051f39x/37x upper 128 bytes of data memory. figure 17.1 illustrates the data memo ry organization of the c8051f39x/ 37x. 17.2.1.1. general purpose registers the lower 32 bytes of data memory, locations 0x00 through 0x1f, may be addressed as four banks of gen- eral-purpose registers. each bank consists of ei ght byte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bi ts in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see desc ription of the psw in sfr definition 15.6). this allows fast context switching when entering subroutines and in terrupt service routines. in direct addressing modes use registers r0 and r1 as index registers. 17.2.1.2. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destinat ion operands as opposed to a byte source or destina- tion). the mcs-51? assembly language allows an alternate notation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22.3h moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 17.2.1.3. stack a programmer's stack can be located anywhere in the 256-byte data memory. the stack area is desig- nated using the stack pointer (sp) sfr. the sp will point to the last lo cation used. the next value pushed on the stack is placed at sp+1 and then sp is incremen ted. a reset initializes t he stack pointer to location 0x07. therefore, the first value pushed on the stack is placed at location 0x08, which is also the first regis- ter (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes. 17.2.2. external ram there are 768 bytes of on-chip ram mapped into the external data memory space. all of these address locations may be accessed using the external move instruction (movx) and the data pointer (dptr), or using movx indirect addressing mode. if the movx in struction is used with an 8-bit address operand (such as @r1), then the high byte of the 16-bit addr ess is provided by the external memory interface con- trol register (emi0cn as shown in sfr definition 17.1 ). note: the movx instructi on is also used for writes to the flash memory. see section ?21. flash memo ry? on page 129 for details. the movx instruction accesses xram by default. memory locations between address 0x0300 a nd 0x03ff will all read back 0x00. for a 16-bit movx operation (@dptr), the upper 6 bits of the 16-bit external data memory address word are "don't cares". as a result, addresses 0x0000 through 0x03ff are mapped modulo style over the entire 64 k external data memory address range. for exam ple, the xram byte at address 0x0000 is shadowed at addresses 0x0400, 0x0800, 0x0c00, 0x1000, etc. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 94 preliminary rev. 0.71 sfr address = 0xaa; sfr page = all pages sfr definition 17.1. emi0cn: exte rnal memory interface control bit76543210 name pgsel type rrrrrr r/w reset 00000000 bit name function 7:2 unused read = 000000b; write = don?t care 1:0 pgsel xram page select. the pgsel field provides the high byte of the 16-bit external data memory address when using an 8-bit movx command, effectively selecting a 256-byte page of ram. since the upper (unused) bits of the register are always zero, the pgsel deter- mines which page of xram is accessed. for example: if pgsel = 0x01, addresses 0x0100 through 0x01ff will be accessed. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 95 c8051f39x/37x 18. device id registers the c8051f39x/37x has sfrs that id entify the device family and derivat ive. these sfrs can be read by firmware at runtime to determine th e capabilities of the mcu that is ex ecuting code. this allows the same firmware image to run on mcus with different memory sizes and peripherals, and dynamically changing functionality to suit the capabilities of that mcu. in order for firmware to i dentify the mcu, it must r ead two sfrs. derivid descri bes the specific derivative within that device family, and revid descr ibes the hardware revision of the mcu. the c8051f39x/37x devices also include four sfrs , sn0 through sn3, that are pre-programmed during production with a unique, 32-bit serial number. the se rial number provides a unique identification number for each device and can be read from the application firm ware. if the serial number is not used in the appli- cation, these four registers can be used as general purpose sfrs. sfr address = 0xab; sfr page = 0 sfr definition 18.1. deriv id: device derivative id bit76543210 name derivid type r reset varies varies varies varies varies varies varies varies bit name function 7:0 derivid derivative id. this read-only register returns th e 8-bit derivative id, which can be used by firmware to identify wh ich device in the product family is being used. 0xd0: c8051f390 0xd1: c8051f391 0xd2: c8051f392 0xd3: c8051f393 0xd4: c8051f394 0xd5: c8051f395 0xd6: c8051f396 0xd7: c8051f397 0xd8: c8051f398 0xd9: c8051f399 0xe0: c8051f370 0xe1: c8051f371 0xe4: c8051f374 0xe5: c8051f375 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 96 preliminary rev. 0.71 sfr address = 0xac; sfr page = 0 sfr address = 0xae; sfr page = f sfr definition 18.2. revision: device revision id bit76543210 name revision type r reset varies varies varies varies varies varies varies varies bit name function 7:0 revision device revision. this read-only register returns the 8-bit revision id. for example: 0x00 = revision a. sfr definition 18.3. sn3: serial number byte 3 bit76543210 name sn3 type r reset varies varies varies varies varies varies varies varies bit name function 7:0 sn3 serial number byte 3. this read-only register returns the msb (byte 3) of the serial num- ber. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 97 c8051f39x/37x sfr address = 0xad; sfr page = f sfr address = 0xac; sfr page = f sfr definition 18.4. sn2: serial number byte 2 bit76543210 name sn2 type r reset varies varies varies varies varies varies varies varies bit name function 7:0 sn2 serial number byte 2. this read-only register returns the byte 2 of the serial number. sfr definition 18.5. sn1: serial number byte 1 bit76543210 name sn1 type r reset varies varies varies varies varies varies varies varies bit name function 7:0 sn1 serial number byte 1. this read-only register returns byte 1 of the serial number. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 98 preliminary rev. 0.71 sfr address = 0xab; sfr page = f sfr definition 18.6. sn0: serial number byte 0 bit76543210 name sn0 type r reset varies varies varies varies varies varies varies varies bit name function 7:0 sn0 serial number byte 0. this read-only register returns the lsb (byte 0) of the serial num- ber. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 99 c8051f39x/37x 19. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfrs). the sfrs provide control and data exchang e with the c8051f39x/37x's resources and peripher- als. the cip-51 controller core duplicates the sfrs found in a typical 8051 implementation as well as implementing additional sfrs used to configure an d access the sub-systems unique to the c8051f39x/ 37x. this allows the addition of new functionality while retaining compatibility with the mcs-51? instruc- tion set. table 19.2 lists the sfrs implemented in the c8051f39x/37x device family. the sfr registers are accessed anytime the direct ad dressing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x0 or 0x8 (e.g. p0, tcon, scon0, ie, etc.) are bit- addressable as well as byte-addressable. all ot her sfrs are byte-addressable only. unoccupied addresses in the sfr space are reserved for future us e. accessing these areas will have an indeterminate effect and should be avoided. refer to the corresponding pages of the data sheet, as indicated in table 19.3, for a detailed description of each register. 19.1. sfr paging the cip-51 features sfr paging, allowing the device to map many sfrs into the 0x80 to 0xff memory address space. the sfr memory space has 256 pages. in this way, each memory location from 0x80 to 0xff can access up to 256 sfrs. the c8051f39x/37x devices utilize two sfr page s: 0x0, and 0xf. most sfrs are available on both pages. sfr pages are selected using the specia l function register page selection register, sfrpage. the procedure fo r reading and writing an sfr is as follows: 1. select the appropriate sfr page number using the sfrpage register. 2. use direct accessing mode to read or write t he special function register (mov instruction). 19.2. interrupts and automatic sfr paging when an interrupt occurs, the current sfrpage is pushed onto the sfr page stack. upon execution of the reti instruction, the sfr page is automatically restored to the sfr page in use prior to the interrupt. this is accomplished via a five-byte sfr page stack , depicted in figure 19.1 . firmware can read any ele- ment of the sfr page stack by setting the sfr pa ge stack index (sfrpgidx) in the sfr page control register (sfrpgcn) and reading the sfrstack register: table 19.1. sfr page stack sfrpgidx value sfrstack contains 000b value of the first/top* byte of the stack 001b value of the second byte of the stack 011b value of the third byte of the stack 010b value of the forth byte of the stack 100b value of the fifth/bottom byte of the stack *note: the first/top byte of the stack can also be directly accessed by reading sfrpage. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 100 preliminary rev. 0.71 figure 19.1. sfr page stack upon an interrupt, hardware performs the five following operations: 1. the value (if any) in the sfrpgidx = 011b location is pushed to the sfrpage = 100b location. 2. the value (if any) in the sfrp gidx = 010b location is pushed to the sfrpage = 011b location. 3. the value (if any) in the sfrp gidx = 001b location is pushed to the sfrpage = 010b location. 4. the current sfrpage value is pushed to the sfrpgidx = 001b location in the stack. 5. sfrpage is set to the page corresponding to the flag which generated the interrupt. on a return from interr upt, hardware performs the four following operations: 1. the sfr page stack is popped resulting in the value in the sfrpgidx = 001b location returning to the sfrpage register, thereby restoring the sfr pa ge context without software intervention. 2. the value in the sfrpgidx = 010b location of th e stack is placed in the sfrpgidx = 001b location. 3. the value in the sfrpgidx = 011b location of th e stack is placed in the sfrpgidx = 010b location. 4. the value in the sfrpgidx = 100b location of the stack is placed in the sfrpgidx = 011b location. automatic switching of the sfr page by hardware upon interrupt entries and exits may be enabled or dis- abled using the sfr automatic page control enable bit (sfrpgen) lo cated in sfrpgcn. the automatic sfr page switching is enabled after a reset until disabled by firmware. 000 001 010 011 100 sfrpage sfrstack interrupt logic sfrpgen sfr page stack sfrpgcn sfrpgidx2 sfrpgidx1 sfrpgidx0 sfrpgen www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 101 c8051f39x/37x 19.3. sfr page stack example in this example, the sfr control re gister is left in the default enabled state (sfrpgen set to 1), and the core is executing in-line code that is writing values to temperature se nsor control register (ts0cn). the device is also using the spi peripheral (spi0) an d the programmable counter array (pca0) peripheral to generate a pwm output. the pca is timing a critical co ntrol function in its interrupt service routine, there- fore, its associated isr is set to high priority. at th is point, the sfr page is set to 0x0f to access the ts0cn sfr. see figure 19.2. figure 19.2. sfr page stack while using sfr page 0x0f to access ts0cn 000 001 010 011 100 sfrpage = 0x0f (ts0cn) sfrpgidx[2:0] sfrstack www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 102 preliminary rev. 0.71 the spi0 interrupt occurs while the core executes in-line code by writing a value to ts0cn. the core vec- tors to the spi0 isr and pushes the current sfr page value (in this case sfr page 0x0f for ts0cn) into the 001b sfrpgidx location in the sfr page stack. also, the core automatically places the sfr page (0x00) needed to access the spi0?s special function re gisters into the sfrpage register. see figure 19.3. sfrpage is considered the top of the sfr page stac k. software may switch to any sfr page by writing a new value to the sfrpage register at any time during the spi0 isr. figure 19.3. sfr page stack after spi0 interrupt occurs 000 001 010 011 100 sfrpgidx[2:0] sfrstack sfrpage = 0x00 (spio0) 0x0f (ts0cn) sfrpage is pushed to sfrpgidx = 001b location 1) sfrpage automatically set to 0x00 on spi0 interrupt 2) www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 103 c8051f39x/37x while in the spi0 isr, a pc a interrupt occurs. recall th e pca interrupt is configured as a high priority interrupt, while the spi0 interr upt is configured as a low priority interrup t. thus, the cip-51 will now vector to the high priority pca isr. upon doing so, the value that was in the sfrpgidx = 001b location before the pca interrupt (in this case sfr page 0x0f for ts 0cn) is pushed down to the sfrpgidx = 010b loca- tion. likewise, the value that was in the sfrpage r egister before the pca interrupt (sfr page 0x00 for spi0) is pushed down the stack into the sfrpgidx = 001b location. la stly, the cip-51 will automatically places the sfr page needed to access the pca0?s sp ecial function registers into the sfrpage register, sfr page 0x00. see figure 19.4. figure 19.4. sfr page stack upon pca interrupt occurring during a spi0 isr 000 001 010 011 100 sfrpgidx[2:0] sfrstack sfrpage = 0x00 (pca0) 0x0f (ts0cn) 0x00 (spi0) sfrpage is pushed to sfrpgidx = 001b location 2) sfrpage automatically set to 0x00 on pca0 interrupt 3) value at sfrpgidx = 001b location is pushed to sfrpgidx = 010b location 1) www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 104 preliminary rev. 0.71 on exit from the pca0 inte rrupt service routine, the ci p-51 will return to the spi0 isr. on execution of the reti instruction, sfr page 0x00 used to access the pc a0 registers will be automa tically popped off of the sfr page stack, and the contents at the sfrpgidx = 001b location will be moved to the sfrpage reg- ister. software in the spi0 isr can continue to access sfrs as it did prior to the pca interrupt. likewise, the contents at the sfrpgidx = 010b location are moved to the sfrpgidx = 001b location. recall this was the sfr page value 0x0f being used to access ts0cn before the spi0 interrupt occurred. see figure 19.5. figure 19.5. sfr page stack upon return from pca0 interrupt 000 001 010 011 100 sfrpgidx[2:0] sfrstack sfrpage = 0x00 (spi0) 0x0f (ts0cn) value at sfrpgidx = 001b location is popped to sfrpgidx = 010b location 3) sfr page 0x00 from pca0 isr automatically popped off on return from interrupt 1) value at sfrpgidx = 001b location is popped to sfrpage 2) www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 105 c8051f39x/37x on the execution of the re ti instruction in the spi0 isr, the valu e in sfrpage register is overwritten with the contents at the sfrpgidx = 001b location. th e cip-51 may now access the ts0cn register as it did prior to the interrupts occurring. see figure 19.6. figure 19.6. sfr page stack upon return from spi0 interrupt push operations on the sfr page stac k only occur on interrupt service, and pop operations only occur on interrupt exit (execution on the reti instruction). the automatic switching of the sfrpage and operation of the sfr page stack as described above can be disabled in software by clearing the sfr automatic page enable bit (sfrpgen) in the sf r page control register (sfrpgcn). 000 001 010 011 100 sfrpgidx[2:0] sfrstack sfrpage = 0x0f (ts0cn) sfr page 0x00 from spi0 isr automatically popped off on return from interrupt 1) value at sfrpgidx = 001b location is popped to sfrpage 2) www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 106 preliminary rev. 0.71 sfr address = 0xa7; sfr page = all pages sfr definition 19.1. sfrpage: sfr page bit7654321 0 name sfrpage[7:0] type r/w reset 0000000 0 bit name function 7:0 sfrpage[7:0] sfr page bits. represents the sfr page the c8051 core uses when reading or modifying sfrs. write: sets the sfr page. read: byte is the sfr page the c8051 core is using. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 107 c8051f39x/37x sfr address = 0xcf; sfr page = all pages sfr definition 19.2. sfrpg cn: sfr page control bit7654321 0 name sfrpgidx[2:0] sfrpgen type r/w r/w r/w r/w r/w r/w reset 0000000 1 bit name function 7 reserved must write 0b 6:4 sfrpgidx[2:0] sfr page stack index. this field can be used to access the sfrpage values stored in the sfr page stack. it selects whic h level of the stack is accessi- ble when reading the sfrstack register. 000: sfrstack contains the value of sfrpage, the first/top byte of the sfr page stack 001: sfrstack contains the value of the second byte of the sfr page stack 010: sfrstack contains the value of the third byte of the sfr page stack 011: sfrstack contains the value of the forth byte of the sfr page stack 100: sfrstack contains the value of the fifth/bottom byte of the sfr page stack 101: invalid index 11x: invalid index 3:1 reserved must write 000b 0sfrpgen sfr automatic page control enable. this bit is used to enable automatic page switching on isr entry/ exit. when set to 1, the curr ent sfrpage value will be pushed onto the sfr page stack, and sfrpage will be set to the page corresponding to the flag which generated the interrupt; upon isr exit, hardware will pop the value from the sfr page stack and restore sfrpage. 0: disable automatic sfr paging. 1: enable automatic sfr paging. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 108 preliminary rev. 0.71 sfr address = 0xd3; sfr page = f sfr definition 19.3. sfrstack: sfr page stack bit7654321 0 name sfrstack type r reset 0000000 0 bit name function 7:0 sfrstack sfr page stack. this register is used to access the contents of the sfr page stack. sfrpgidx in the sfrpgcn register con- trols which level of the sta ck this register will access. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 109 c8051f39x/37x table 19.2. special function register (sfr) memory map address page 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) f8 spi0cn pca0l pca0h pca0cpl0 pca0cph0 p0mat p0mask vdm0cn f0 b p0mdin p1mdin p2mdin ckcon1 eip1 pca0pwm e8 adc0cn pca0cpl1 pca0cph1 pca0cpl2 pca0cph2 p1mat p1mask rstsrc e0 0 acc xbr0 xbr1 osclcn it01cf eie1 smb0adm f smb1adm d8 pca0cn pca0md pca0cpm0 pca0cpm1 pca0cpm2 crc0auto crc0cnt crc0cn d0 0 psw ref0cn ts0datl ts0dath p0skip p1skip p2skip smb0adr f ts0cn sfrstack smb1adr c8 tmr2cn reg0cn tmr2rll tmr2rlh tmr2l tmr2h pca0clr sfrpgcn tmr5cn tmr5rll tmr5rlh tmr5l tmr5h c0 0 smb0cn smb0cf smb0dat adc0gtl adc0gth adc0ltl adc0lth smbtc f smb1cn smb1cf smb1dat b8 0 ip ida0cn amx0n amx0p adc0cf adc0l adc0h eip2 f ida1cn b0 oscxcn oscicn oscicl pfe0cn flscl flkey a8 0 ie clksel emi0cn derivid revision eie2 f sn0 sn1 sn2 sn3 a0 p2 spi0cfg spi0ckr spi0dat p0md out p1mdout p2mdout sfrpage 98 scon0 sbuf0 crc0flip cpt0cn crc0in cpt0md crc0dat cpt0mx 90 0 p1 tmr3cn tmr3rll tmr3rlh tmr3l tmr3h ida0l ida0h f tmr4cn tmr4rll tmr4rlh tmr4l tmr4h ida1l ida1h 88 tcon tmod tl0 tl1 th0 th1 ckcon psctl 80 p0 sp dpl dph iph eip1h eip2h pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) notes: 1. sfr addresses ending in 0x0 or 0x8 are bit-addressable locations and can be used with bitwise instructions. 2. unless indicated otherwise, sfrs are available on both page 0 and page f. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 110 preliminary rev. 0.71 table 19.3. special function registers sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address sfr page description page acc 0xe0 all pages accumulator 87 adc0cf 0xbc all pages adc0 configuration 53 adc0cn 0xe8 all pages adc0 control 55 adc0gth 0xc4 all pages adc0 greate r-than compare high 56 adc0gtl 0xc3 all pages adc0 greater-than compare low 56 adc0h 0xbe all pages adc0 high 54 adc0l 0xbd all pages adc0 low 54 adc0lth 0xc6 all pages adc0 less-th an compare word high 57 adc0ltl 0xc5 all pages adc0 less-than compare word low 57 amx0n 0xba all pages amux0 negative channel select 61 amx0p 0xbb all pages amux0 posi tive channel select 60 b 0xf0 all pages b register 88 ckcon 0x8e all pages clock control 241 ckcon1 0xf4 all pages clock control 1 242 clksel 0xa9 all pages clock select 163 cpt0cn 0x9b all pages comparator0 control 76 cpt0md 0x9d all pages comparator0 mode selection 77 cpt0mx 0x9f all pages comparator0 mux selection 79 crc0auto 0xdd all pages crc0 automatic control 150 crc0cn 0xdf all pages crc0 control 148 crc0cnt 0xde all pages crc0 automatic flash sector count 151 crc0dat 0x9e all pages crc0 data output 149 crc0flip 0x9a all pages crc0 bit flip 152 crc0in 0x9c all pages crc0 data input 149 derivid 0xab 0 device derivative id 95 dph 0x83 all pages data pointer high 86 dpl 0x82 all pages data pointer low 86 eie1 0xe6 all pages extended interrupt enable 1 121 eie2 0xaf all pages extended interrupt enable 2 124 eip1 0xf6 all pages extended interrupt priority 1 122 eip1h 0x85 all pages extended interrupt priority 1 high 123 eip2 0xbf all pages extended interrupt priority 2 125 eip2h 0x86 all pages extended interrupt priority 2 high 125 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 111 c8051f39x/37x emi0cn 0xaa all pages external memory interface control 94 flkey 0xb7 all pages flash lock and key 136 flscl 0xb6 all pages flash scale 137 ida0cn 0xb9 0 current mode dac0 control 67 ida0h 0x97 0 current mode dac0 high 68 ida0l 0x96 0 current mode dac0 low 68 ida1cn 0xb9 f current mode dac1 control 69 ida1h 0x97 f current mode dac1 high 70 ida1l 0x96 f current mode dac1 low 70 ie 0xa8 all pages interrupt enable 118 ip 0xb8 all pages interrupt priority 119 iph 0x84 all pages interrupt priority high 120 it01cf 0xe4 all pages int0/int1 configuration 127 oscicl 0xb3 all pages internal os cillator calibration 164 oscicn 0xb2 all pages internal oscillator control 165 osclcn 0xe3 all pages low-frequency oscillator control 166 oscxcn 0xb1 all pages external oscillator control 170 p0 0x80 all pages port 0 latch 184 p0mask 0xfe all pages port 0 mask configuration 181 p0mat 0xfd all pages port 0 match configuration 182 p0mdin 0xf1 all pages port 0 input mode configuration 184 p0mdout 0xa4 all pages port 0 output mode configuration 185 p0skip 0xd4 all pages port 0 skip 185 p1 0x90 all pages port 1 latch 186 p1mask 0xee all pages port 1mask configuration 182 p1mat 0xed all pages port 1 match configuration 183 p1mdin 0xf2 all pages port 1 input mode configuration 186 p1mdout 0xa5 all pages port 1 output mode configuration 187 p1skip 0xd5 all pages port 1 skip 187 p2 0xa0 all pages port 2 latch 188 p2mdin 0xf3 all pages port 2 input mode configuration 188 p2mdout 0xa6 all pages port 2 output mode configuration 189 p2skip 0xd6 all pages port 2 skip 189 pca0clr 0xce all pages pca comparator clear control 291 table 19.3. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address sfr page description page www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 112 preliminary rev. 0.71 pca0cn 0xd8 all pages pca control 288 pca0cph0 0xfc all pages pca capture 0 high 294 pca0cph1 0xea all pages pca capture 1 high 294 pca0cph2 0xec all pages pca capture 2 high 294 pca0cpl0 0xfb all pages pca capture 0 low 294 pca0cpl1 0xe9 all pages pca capture 1 low 294 pca0cpl2 0xeb all pages pca capture 2 low 294 pca0cpm0 0xda all pages pca module 0 mode register 292 pca0cpm1 0xdb all pages pca module 1 mode register 292 pca0cpm2 0xdc all pages pca module 2 mode register 292 pca0h 0xfa all pages pca counter high 293 pca0l 0xf9 all pages pca counter low 293 pca0md 0xd9 all pages pca mode 289 pca0pwm 0xf7 all pages pca pwm configuration 290 pcon 0x87 all pages power control 161 pfe0cn 0xb5 all pages prefetch engine control 90 psctl 0x8f all pages program store r/w control 135 psw 0xd0 all pages program status word 89 ref0cn 0xd1 all pages voltage reference control 72 reg0cn 0xc9 all pages voltage regulator control 73 revision 0xac 0 device revision 96 rstsrc 0xef all pages reset source configuration/status 158 sbuf0 0x99 all pages uart0 data buffer 224 scon0 0x98 all pages uart0 control 223 sfrpage 0xbf all pages sfr page 106 sfrpgcn 0xbf all pages sfr page control 107 sfrstack 0xbf f sfr page stack 108 smb0adm 0xe7 0 smbus0 slave address mask 204 smb0adr 0xd7 0 smbus0 slave address 203 smb0cf 0xc1 0 smbus0 configuration 196 smb0cn 0xc0 0 smbus0 control 200 smb0dat 0xc2 0 smbus0 data 207 smb1adm 0xe7 f smbus1 slave address mask 206 smb1adr 0xd7 f smbus1 slave address 205 table 19.3. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address sfr page description page www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 113 c8051f39x/37x smb1cf 0xc1 f smbus1 configuration 197 smb1cn 0xc0 f smbus1 control 201 smb1dat 0xc2 f smbus1 data 208 smbtc 0xc7 all pages smbus timing control 198 sn0 0xab f serial number byte 0 98 sn1 0xac f serial number byte 1 97 sn2 0xad f serial number byte 2 97 sn3 0xae f serial number byte 3 96 sp 0x81 all pages stack pointer 87 spi0cfg 0xa1 all pages spi configuration 233 spi0ckr 0xa2 all pages spi clock rate control 235 spi0cn 0xf8 all pages spi control 234 spi0dat 0xa3 all pages spi data 236 tcon 0x88 all pages timer/counter control 247 th0 0x8c all pages timer/counter 0 high 250 th1 0x8d all pages timer/counter 1 high 250 tl0 0x8a all pages timer/counter 0 low 249 tl1 0x8b all pages timer/counter 1 low 249 tmod 0x89 all pages timer/counter mode 248 tmr2cn 0xc8 0 timer/counter 2 control 254 tmr2h 0xcd 0 timer/counter 2 high 256 tmr2l 0xcc 0 timer/counter 2 low 255 tmr2rlh 0xcb 0 timer/counter 2 reload high 255 tmr2rll 0xca 0 timer/counter 2 reload low 255 tmr3cn 0x91 0 timer/counter 3 control 260 tmr3h 0x95 0 timer/counter 3 high 262 tmr3l 0x94 0 timer/counter 3 low 261 tmr3rlh 0x93 0 timer/counter 3 reload high 261 tmr3rll 0x92 0 timer/counter 3 reload low 261 tmr4cn 0x91 f timer/counter 4 control 265 tmr4h 0x95 f timer/counter 4 high 267 tmr4l 0x94 f timer/counter 4 low 266 tmr4rlh 0x93 f timer/counter 4 reload high 266 tmr4rll 0x92 f timer/counter 4 reload low 266 table 19.3. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address sfr page description page www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 114 preliminary rev. 0.71 tmr5cn 0xc8 f timer/counter 5 control 270 tmr5h 0xcd f timer/counter 5 high 272 tmr5l 0xcc f timer/counter 5 low 271 tmr5rlh 0xcb f timer/counter 5 reload high 271 tmr5rll 0xca f timer/counter 5 reload low 271 ts0cn 0xd2 f temperature sensor control 46 ts0dath 0xd3 0 temperature sensor data high 47 ts0datl 0xd2 0 temperature sensor data low 47 vdm0cn 0xff all pages v dd monitor control 156 xbr0 0xe1 all pages port i/o crossbar control 0 179 xbr1 0xe2 all pages port i/o crossbar control 1 180 table 19.3. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address sfr page description page www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 115 c8051f39x/37x 20. interrupts the c8051f39x/37x includes an extended interrupt s ystem supporting multiple interrupt sources with four priority levels. the allocation of interrupt sources between on-chip peri pherals and external input pins var- ies according to the specific version of the device. ea ch interrupt source has one or more associated inter- rupt-pending flag(s) located in an sfr. when a peri pheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. if interrupts are enabled for the source, an interrupt re quest is generated when the interrupt-pending flag is set. as soon as execution of the current instructio n is complete, the cpu generates an lcall to a prede- termined address to begin execution of an interrupt service routine (isr). each isr must end with an reti instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (t he interrupt-pending flag is set to logic 1 regard- less of the interrupt's enable/disable state.) each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an sfr (ie, eie1, and eie2). however, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic 1 before the individual interrup t enables are recognized. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. note: any instruction that clears a bit to disable an inte rrupt should be immediatel y followed by an instruc- tion that has two or more opcode bytes. using ea (global interrupt enable) as an example: // in 'c': ea = 0; // clear ea bit. ea = 0; // this is a dummy instruction with two-byte opcode. ; in assembly: clr ea ; clear ea bit. clr ea ; this is a dummy instruction with two-byte opcode. for example, if an interrupt is posted during the exec ution phase of a "clr ea" opcode (or any instruction which clears a bit to disable an interrupt source), an d the instruction is followed by a single-cycle instruc- tion, the interrupt may be taken. however, a read of the enable bit will return a '0' inside the interrupt ser- vice routine. when the bit-clearing opcode is followed by a multi-cycle instruction, the interrupt will not be taken. some interrupt-pending flags are automatically cleare d by the hardware when the cpu vectors to the isr. however, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interr upt request will be gen erated immediately and the cpu will re-enter the isr after the completion of the next instruction. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 116 preliminary rev. 0.71 20.1. mcu interrupt sources and vectors the c8051f39x/37x mcus support 18 interrupt sources. software can simulate an interrupt by setting any interrupt-pending flag to logic 1. if interrupts are enabled fo r the flag, an in terrupt request w ill be generated and the cpu will vector to the isr address associated wit h the interrupt- pending flag. mcu interrupt sources, associated vector addresses, priority order and control bits are summarized in table 20.2. refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and t he behavior of its interrupt-pending flag(s). 20.1.1. interr upt priorities each interrupt source can be individually programmed to one of four priority levels. this differs from the traditional two priority leve ls on the 8051 core. however, the implementation of the extra levels is back- wards-compatible wit h legacy 8051 code. an interrupt service routine can be preempted by any interrupt of higher priority. interrupts at the highest priority level cannot be preempted. each interrupt has two associated priority bits which are used to config- ure the priority level. for backward s compatibility, the bits are spread across two different registers. the lsbs of the priority setting are stored in the ip, eip1 and eip2 registers, while the msbs are store in the iph, eip1h and eip2h registers. pr iority levels according to the msb and lsb are decoded in table 20.1. the lowest priority setting is the de fault for all interrupts. if two or more interrupts are recognized simulta- neously, the interrupt with the highest priority is serviced first. if both interrupts ha ve the same priority level, a fixed priority order is used to arbitrate, given in ta ble 20.2. if legacy 8051 operation is desired, the bits of the ?high? priority registers (iph, eip1h and eip2h) should all be configured to 0 (this is the reset value of these registers). table 20.1. configurable interrupt priority decoding 20.1.2. interr upt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each sys tem clock cycle. therefore, the fastest possible response time is 5 system clock cycles: 1 clock cycle to detect the interrup t and 4 clock cycles to complete the lcall to the isr. if an interrupt is pending when a reti is execut ed, a single instruction is executed before an lcall is made to service the pending interrupt. therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the cpu is performing an reti instruct ion followed by a div as the next instructio n. in this case, th e response time is 18 system clock cycles: 1 clock cycle to detect the in terrupt, 5 clock cycles to execute the reti, 8 clock cycles to complete the div instruction and 4 clock cycl es to execute the lcall to the isr. if the cpu is executing an isr for an interr upt with equal or higher pr iority, the new interrupt will not be serviced until the current isr comple tes, including the reti and following instruction. if more than one interrupt is pending when the cpu exits an isr, the cpu will service the next highest priority inte rrupt that is pending. priority msb (from iph, eip1h or eip2h) priority lsb (from ip, eip1 or eip2) priority level 0 0 priority 0 (lowest priority, default) 0 1 priority 1 1 0 priority 2 1 1 priority 3 (highest priority) www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 117 c8051f39x/37x table 20.2. interrupt summary interrupt source interrupt vector priority order pending flags bit addressable? cleared by hw? enable flag reset 0x0000 top none n/a n/a always enabled external interrupt 0 (int0 ) 0x0003 0 ie0 (tcon.1) y y ex0 (ie.0) timer 0 overflow 0x000b 1 tf0 (tcon.5) y y et0 (ie.1) external interrupt 1 (int1 ) 0x0013 2 ie1 (tcon.3) y y ex1 (ie.2) timer 1 overflow 0x001b 3 tf1 (tcon.7) y y et1 (ie.3) uart0 0x0023 4 ri0 (scon0.0) ti0 (scon0.1) y n es0 (ie.4) timer 2 overflow 0x002b 5 tf2h (tmr2cn.7) tf2l (tmr2cn.6) y n et2 (ie.5) spi0 0x0033 6 spif (spi0cn.7) wcol (spi0cn.6) modf (spi0cn.5) rxovrn (spi0cn.4) y n espi0 (ie.6) smb0 0x003b 7 si (smb0cn.0) y n esmb0 (eie1.0) port match 0x0043 8 none n/a n/a emat (eie1.1) adc0 window compare 0x004b 9 ad0wint (adc0cn.3) y n ewadc0 (eie1.2) adc0 conversion com- plete 0x0053 10 ad0int (adc0cn.5) y n eadc0 (eie1.3) programmable counter array 0x005b 11 cf (pca0cn.7) ccfn (pca0cn.n) covf (pca0pwm.6) y n epca0 (eie1.4) comparator0 0x0063 12 cp0fif (cpt0cn.4) cp0rif (cpt0cn.5) n n ecp0 (eie1.5) reserved 0x006b 13 n/a n/a n/a n/a timer 3 overflow 0x0073 14 tf3h (tmr3cn.7) tf3l (tmr3cn.6) n n et3 (eie1.7) smb1 0x007b 15 si (smb0cn.0) y n esmb0 (eie2.0) timer 4 overflow 0x0083 16 tf4h (tmr4cn.7) tf4l (tmr4cn.6) y n et4 (eie2.1) timer 5 overflow 0x008b 17 tf5h (tmr5cn.7) tf5l (tmr5cn.6) n n et5 (eie2.2) precision temp sensor 0x0093 18 ts0dn (ts0cn.6) n n epts (eie2.3) www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 118 preliminary rev. 0.71 20.2. interrupt re gister descriptions the sfrs used to enable the interrupt sources and set their priority level are described in this section. refer to the data sheet section associated with a pa rticular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). sfr address = 0xa8; sfr page = a ll pages; bit-addressable sfr definition 20.1. ie: interrupt enable bit76543210 name ea espi0 et2 es0 et1 ex1 et0 ex0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7ea enable all interrupts. globally enables/disables all interrupts. it overrides individual interrupt mask settings. 0: disable all interrupt sources. 1: enable each interrupt according to its individual mask setting. 6 espi0 enable serial peripheral interface (spi0) interrupt. this bit sets the masking of the spi0 interrupts. 0: disable all spi0 interrupts. 1: enable interrupt requests generated by spi0. 5et2 enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests gener ated by the tf2l or tf2h flags. 4 es0 enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable uart0 interrupt. 3et1 enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all timer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. 2 ex1 enable external interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the /int1 input. 1et0 enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all timer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag. 0 ex0 enable external interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the int0 input. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 119 c8051f39x/37x sfr address = 0xb8; sfr page = a ll pages; bit-addressable sfr definition 20.2. ip: interrupt priority bit76543210 name pspi0 pt2 ps0 pt1 px1 pt0 px0 type r r/w r/w r/w r/w r/w r/w r/w reset 10000000 bit name function 7 unused read = 1, write = don't care. 6 pspi0 serial peripheral interface (spi 0) interrupt pr iority control lsb. this bit sets the lsb of the prio rity field for the spi0 interrupt. 5pt2 timer 2 interrupt priority control lsb. this bit sets the lsb of the priority field for the timer 2 interrupt. 4 ps0 uart0 interrupt priority control lsb. this bit sets the lsb of the prio rity field for the uart0 interrupt. 3pt1 timer 1 interrupt priority control lsb. this bit sets the lsb of the priority field for the timer 1 interrupt. 2 px1 external interrupt 1 priority control lsb. this bit sets the lsb of the priority field for the external interrupt 1 interrupt. 1pt0 timer 0 interrupt priority control lsb. this bit sets the lsb of the priority field for the timer 0 interrupt. 0 px0 external interrupt 0 priority control lsb. this bit sets the lsb of the priority field for the external interrupt 0 interrupt. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 120 preliminary rev. 0.71 sfr address = 0x84; sfr page = all pages; bit-addressable sfr definition 20.3. iph: interrupt priority high bit76543210 name phspi0 pht2 phs0 pht1 phx1 pht0 phx0 type r r/w r/w r/w r/w r/w r/w r/w reset 10000000 bit name function 7 unused read = 1, write = don't care. 6 phspi0 serial peripheral interface (spi0) interrupt priority control msb. this bit sets the msb of the priority field for the spi0 interrupt. 5pht2 timer 2 interrupt prio rity control msb. this bit sets the msb of the priority field for the timer 2 interrupt. 4phs0 uart0 interrupt priority control msb. this bit sets the msb of the priority field for the uart0 interrupt. 3pht1 timer 1 interrupt pr iority control msb. this bit sets the msb of the priority field for the timer 1 interrupt. 2phx1 external interrupt 1 pr iority control msb. this bit sets the msb of the priority field for the external interrupt 1 inter- rupt. 1pht0 timer 0 interrupt prio rity control msb. this bit sets the msb of the priority field for the timer 0 interrupt. 0phx0 external interrupt 0 pr iority control msb. this bit sets the msb of the priority field for the external interrupt 0 inter- rupt. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 121 c8051f39x/37x sfr address = 0xe6; sfr page = all pages sfr definition 20.4. eie1: ex tended interrupt enable 1 bit76543210 name et3 ecp0 epca0 eadc0 ewadc0 emat esmb0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7et3 enable timer 3 interrupt. this bit sets the masking of the timer 3 interrupt. 0: disable timer 3 interrupts. 1: enable interrupt requests generated by the tf3l or tf3h flags. 6 reserved reserved. must write 0. 5ecp0 enable comparator0 (cp0) interrupt. this bit sets the masking of the cp0 interrupt. 0: disable cp0 interrupts. 1: enable interrupt requests generated by the cp0rif or cp0fif flags. 4epca0 enable programmable counte r array (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pca0 interrupts. 1: enable interrupt requests generated by pca0. 3 eadc0 enable adc0 conversion complete interrupt. this bit sets the masking of the a dc0 conversion complete interrupt. 0: disable adc0 conversi on complete interrupt. 1: enable interrupt requests ge nerated by the ad0int flag. 2 ewadc0 enable window comparison adc0 interrupt. this bit sets the masking of adc0 window comparison interrupt. 0: disable adc0 window comparison interrupt. 1: enable interrupt requests genera ted by adc0 window compare flag (ad0wint). 1emat enable port match interrupts. this bit sets the masking of the port match event interrupt. 0: disable all port match interrupts. 1: enable interrupt requests generated by a port match. 0 esmb0 enable smbus (smb0) interrupt. this bit sets the maskin g of the smb0 interrupt. 0: disable all smb0 interrupts. 1: enable interrupt requests generated by smb0. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 122 preliminary rev. 0.71 sfr address = 0xf6; sfr page = all pages sfr definition 20.5. eip1: extended interrupt priority 1 bit76543210 name pt3 pcp0 ppca0 padc0 pwadc0 pmat psmb0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7pt3 timer 3 interrupt priority control lsb. this bit sets the lsb of the priority field for the timer 3 interrupt. 6 reserved reserved. must write 0. 5pcp0 comparator0 (cp0) interrupt priority control lsb. this bit sets the lsb of the prio rity field for the cp0 interrupt. 4 ppca0 programmable counter array (p ca0) interrupt priority control lsb. this bit sets the lsb of the prio rity field for the pca0 interrupt. 3padc0 adc0 conversion complete interrupt priority control lsb. this bit sets the lsb of the priority field for the adc0 conversion complete interrupt. 2 pwadc0 adc0 window comparator interrupt priority control lsb. this bit sets the lsb of the priority field for the adc0 window interrupt. 1pmat port match interrupt pr iority control lsb. this bit sets the lsb of the priori ty field for the port match event interrupt. 0psmb0 smbus (smb0) interrupt priority control lsb. this bit sets the lsb of the prio rity field for the smb0 interrupt. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 123 c8051f39x/37x sfr address = 0x85; sfr page = all pages sfr definition 20.6. eip1h: exte nded interrupt priority 1 high bit76543 2 10 name pht3 phcp0 phpca0 phadc0 phwadc0 phmat phsmb0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000 0 00 bit name function 7pht3 timer 3 interrupt priority control msb. this bit sets the msb of the priority field for the timer 3 interrupt. 6 reserved reserved. must write 0. 5 phcp0 comparator0 (cp0) interrupt priority control msb. this bit sets the msb of the priority field for the cp0 interrupt. 4phpca0 programmable counter array (pca0) interrupt priority control msb. this bit sets the msb of the prio rity field for the pca0 interrupt. 3 phadc0 adc0 conversion complete in terrupt priority control msb. this bit sets the msb of the priority field for the adc0 conversion complete interrupt. 2 phwadc0 adc0 window comparator interrupt priority control msb. this bit sets the msb of the priority field for the adc0 window interrupt. 1phmat port match interrupt priority control msb. this bit sets the msb of the priori ty field for the port match event interrupt. 0phsmb0 smbus (smb0) interrupt priority control msb. this bit sets the msb of the priority field for the smb0 interrupt. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 124 preliminary rev. 0.71 sfr address = 0xaf; sfr page = all pages sfr definition 20.7. eie2: ex tended interrupt enable 2 bit76543 2 10 name epts et5 et4 esmb1 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000 0 00 bit name function 7:4 reserved must write 0000b. 3 epts enable precision temperature sensor interrupt. this bit sets the masking of th e precision temperature sensor interrupt. 0: disable precision temperature sensor interrupts. 1: enable interrupt requests generated by the precision tempera- ture sensor. 2et5 enable timer 5 interrupt. this bit sets the masking of the timer 5 interrupt. 0: disable timer 5 interrupts. 1: enable interrupt requests generated by the tf5l or tf5h flags. 1et4 enable timer 4 interrupt. this bit sets the masking of the timer 4 interrupt. 0: disable timer 4 interrupts. 1: enable interrupt requests generated by the tf4l or tf4h flags. 0 esmb1 enable smbus (smb1) interrupt. this bit sets the masking of the smb1 interrupt. 0: disable all smb1 interrupts. 1: enable interrupt requests generated by smb1. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 125 c8051f39x/37x sfr address = 0xbf; sfr page = all pages sfr address = 0x86; sfr page = all pages sfr definition 20.8. eip2: extended interrupt priority 2 bit76543210 name ppts pt5 pt4 psmb1 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:4 reserved must write 0000b. 3 ppts precision temperature sensor interrupt priority control lsb. this bit sets the lsb of the priority field for the precision tempera- ture sensor interrupt. 2pt5 timer 5 interrupt priority control lsb. this bit sets the lsb of the priority field for the timer 5 interrupt. 1pt4 timer 4 interrupt priority control lsb. this bit sets the lsb of the priority field for the timer 4 interrupt. 0psmb1 smbus (smb1) interrupt priority control lsb. this bit sets the lsb of the prio rity field for the smb1 interrupt. sfr definition 20.9. eip2h: exte nded interrupt priority 2 high bit76543 2 10 name phpts pht5 pht4 phsmb1 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000 0 00 bit name function 7:4 reserved must write 0000b. 3phpts precision temperature sensor interrupt priority control msb. this bit sets the msb of the priority field for the precision temper- ature sensor interrupt. 2pht5 timer 5 interrupt priority control msb. this bit sets the msb of the priority field for the timer 5 interrupt. 1pht4 timer 4 interrupt priority control msb. this bit sets the msb of the priority field for the timer 4 interrupt. 0phsmb1 smbus (smb1) interrupt priority control msb. this bit sets the msb of the priority field for the smb1 interrupt. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 126 preliminary rev. 0.71 20.3. external interrupts int0 and int1 the int0 and int1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. the in0pl (int0 polarity) and in1pl (int1 polarity) bits in the it01cf register select active high or active low; the it0 and it1 bits in tcon (section ?31.1. timer 0 and timer 1? on page 243) select level or edge sensitive. the table below lis ts the possible configurations. int0 and int1 are assigned to port pins as defined in t he it01cf register (see sfr definition 20.10). note that int0 and int1 port pin assignments are independent of any crossbar assignments. int0 and int1 will monitor their assigned port pi ns without disturbing th e peripheral that was as signed the port pin via the crossbar. to assign a port pin only to int0 and/or int1 , configure the crossbar to skip the selected pin(s). this is accomplished by setting the associat ed bit in register xbr0 (see section ?27.3. priority crossbar decoder? on page 176 for complete details on configuring the crossbar). ie0 (tcon.1) and ie1 (tcon.3) serve as the interrupt-pending flags for the int0 and int1 external inter- rupts, respectively. if an int0 or int1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the cpu vectors to the isr. when configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit (in0pl or in1pl); th e flag remains logic 0 while the input is inactive. the external interrupt source must hold the input active until the interrupt request is recognized. it must then deactivate the interrupt request bef ore execution of the isr completes or another interr upt request will be generated. it0 in0pl int0 interrupt it1 in1pl int1 interrupt 1 0 active low, edge sensitive 1 0 active low, edge sensitive 1 1 active high, edge sensitive 1 1 active high, edge sensitive 0 0 active low, level sensitive 0 0 active low, level sensitive 0 1 active high, level sensitive 0 1 active high, level sensitive www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 127 c8051f39x/37x sfr address = 0xe4; sfr page = all pages sfr definition 20.10. it01cf : int0/int1 configuration bit76543210 name in1pl in1sl[2:0] in0pl in0sl[2:0] type r/w r/w r/w r/w reset 00000001 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 128 preliminary rev. 0.71 bit name function 7in1pl int1 polarity. 0: /int1 input is active low. 1: /int1 input is active high. 6:4 in1sl[2:0] int1 port pin se lection bits. these bits select which port pin is assigned to /int1. note that this pin assignment is independ ent of the crossbar; /int1 will monitor the assigned port pin without disturbing the peripheral that has been assigned the port pin via the crossbar. the cross- bar will not assign the port pin to a peripheral if it is configured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p0.6 111: select p0.7 3in0pl int0 polarity. 0: int0 input is active low. 1: int0 input is active high. 2:0 in0sl[2:0] int0 port pin se lection bits. these bits select which port pin is assigned to int0 . note that this pin assignment is independent of the crossbar; int0 will monitor the assigned port pin without disturbing the peripheral that has been assigned the port pin via the crossbar. the cross- bar will not assign the port pin to a peripheral if it is configured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p0.6 111: select p0.7 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 129 c8051f39x/37x 21. flash memory on-chip, re-programmable flash memory is included fo r program code and non-volatile data storage. the flash memory can be programmed in-system, a single byte at a time, through the c2 interface or by soft- ware using the movx instruct ion. once cleared to logic 0, a flash bit must be erased to set it back to logic 1. flash bytes would typically be erased (set to 0xff) before being reprogrammed. the write and erase operations are automatically timed by hardware for proper execut ion; data polling to determine the end of the write/erase oper ation is not required. code execution is stalled during a flash write/erase oper- ation. refer to section ?7 . electrical characteristics? on page 32 for complete flash memory electrical characteristics. 21.1. programming the flash memory the simplest means of programming the flash memo ry is through the c2 interface using programming tools provided by silicon labs or a third party vendor. this is the only means for programming a non-initial- ized device. for details on the c2 commands to progr am flash memory, see section ?33. c2 interface? on page 295. to ensure the integrity of flas h contents, it is strongly recommended that the on-chip v dd monitor be enabled in any system that includes code that writes and/or erases flash memory from software. see sec- tion 21.4 for more details. 21.1.1. flash lock and key functions flash writes and erases by user so ftware are protected with a lock and key function. th e flash lock and key register (flkey) must be writ ten with the correct key codes, in sequence, be fore flash operations may be performed. the key codes are: 0xa5, 0xf1. the timing does not matter, but the codes must be written in order. if the key codes are written out of or der, or the wrong codes are written, flash writes and erases will be disabled until the next system reset. flash writes and eras es will also be disabled if a flash write or erase is attempted before the key codes have been written properly. the flash lock resets after each write or erase; the key codes must be writte n again before a following flash operation can be per- formed. the flkey register is det ailed in sfr definition 21.2. 21.1.2. flash erase procedure the flash memory can be programmed by software using the movx write instru ction with the address and data byte to be programmed provided as normal operands. before writing to flash memory using movx, flash write operations must be enabled by: (1) setting the pswe program store write enable bit (psctl.0) to logic 1 (this directs the movx writes to target flash memory); and (2) writing the flash key codes in sequence to the flash lock register (flkey). the pswe bit remains set until cleared by soft- ware. a write to flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits to logic 1 in flash. a byte location to be programmed should be erased before a new value is written. the flash memory is organized in 512-byte pages. th e erase operation applies to an entire page (setting all bytes in the page to 0xff). to erase an en tire 512-byte page, perform the following steps: 1. disable interrupts (recommended). 2. set thepsee bit (register psctl). 3. set the pswe bit (register psctl). 4. write the first key code to flkey: 0xa5. 5. write the second key code to flkey: 0xf1. 6. using the movx instruction, write a data byte to any location within the 512-byte page to be erased. 7. clear the pswe and psee bits. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 130 preliminary rev. 0.71 21.1.3. flash write procedure flash bytes are programmed by software with the following sequence: 1. disable interrupts (recommended). 2. erase the 512-byte flash page containing the ta rget location, as described in section 21.1.2. 3. set the pswe bit (register psctl). 4. clear the psee bit (register psctl). 5. write the first key code to flkey: 0xa5. 6. write the second key code to flkey: 0xf1. 7. using the movx instruction, write a single data byte to the desired location within the 512-byte sector. 8. clear the pswe bit. steps 5?7 must be repeated for each byte to be written. after flash writes are complete, pswe should be cleared so that movx instructions do not target program memory. 21.2. non-volati le data storage the flash memory can be used for non-volatile data storage as well as program code. this allows data such as calibration coefficients to be calculated and stored at run time. data is written using the movx write instruction and read using the movc instructi on. note: movx read instructions always target xram. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 131 c8051f39x/37x 21.3. security options the cip-51 provides security options to protect the flash memory from inadvertent modification by soft- ware as well as to prevent the viewing of proprietary program code and constants. the program store write enable (bit pswe in register psctl) and th e program store erase enable (bit psee in register psctl) bits protect the flash memory from accidental modification by software. pswe must be explicitly set to ?1? before software can modify the flash me mory; both pswe and psee must be set to ?1? before software can erase flash memory. additional security features prevent proprietary program code and data constants from being read or altered across the c2 interface. a security lock byte located in flash user space offers protection of the flash program memory from access (reads, writes, or erases) by unprotected code or the c2 interface. see section ?17. memory orga- nization? on page 91 for the location of the security byte. the flash security mechanism allows the user to lock n 512-byte flash pages, starting at page 0 (addresses 0x0000 to 0x01ff), where n is the 1?s comple- ment number represented by the security lock byte. note that the page containing the flash security lock byte is unlocked when no other flash pages are locked (all bits of the lock byte are ?1?) and locked when any other flash pages are locked (any bit of the lock byte is ?0?). an example is shown in figure 21.1. figure 21.1. security byte decoding the level of flash security depends on the flash access method. the three flash access methods that can be restricted are reads, writes, an d erases from the c2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. table 21.1 summarizes the flash security features of the c8051f39x/37x devices. table 21.1. flash security summary action c2 debug interface user firmware executing from: an unlocked page a locked page read, write or erase unlocked pages (except page with lock byte) permitted permitted permitted read, write or erase locked pages (except page with lock byte) not permitted flash error reset permitted read or write page containing lock byte (if no pages are locked) permitted permitted permitted read or write page containing lock byte (if any page is locked) not permitted flash error reset permitted read contents of lock byte (if no pages are locked) permitted permitted permitted read contents of lock byte (if any page is locked) not permitted flash error reset permitted erase page containing lock byte (if no pages are locked) permitted flash error re set flash error reset security lock byte: 11111101b 1s complement: 00000010b flash pages locked: 3 (first two flash pages + lock byte page) www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 132 preliminary rev. 0.71 erase page containing lock byte?unlock all pages (if any page is locked) c2 device erase only flash error reset flash error reset lock additional pages (change 1s to 0s in the lock byte) not permitted flash error reset flash error reset unlock individual pages (change 0s to 1s in the lock byte) not permitted flash error reset flash error reset read, write or erase reserved area not perm itted flash error rese t flash error reset c2 device erase?erases all flash pages in cluding the page containing the lock byte. flash error reset ?not permitted; causes flash erro r device reset (ferror bi t in rstsrc is '1' after reset). - all prohibited operations that are performed via the c2 interface are ignored (do not cause device reset). - locking any flash page also locks th e page containing the lock byte. - once written to, the lock byte cannot be modifi ed except by performing a c2 device erase. - if user code writes to the lock byte, the lock does not take effect until the next device reset. table 21.1. flash security summary www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 133 c8051f39x/37x 21.4. flash write and erase guidelines any system which contains routines which write or er ase flash memory from software involves some risk that the write or erase ro utines will execute unin tentionally if the cpu is op erating outside its specified operating range of v dd , system clock frequency, or temperature. this accidental execution of flash modi- fying code can result in alteration of flash memory contents causing a system failure that is only recover- able by re-flashing the code in the device. the following guide lines are recommended for any system which contains routines which write or erase flash from code. 21.4.1. v dd maintenance and the v dd monitor 1. if the system power supply is subject to voltage or current "spikes," add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the absolute maximum ratings table are not exceeded. 2. make certain that the minimum v dd rise time specification of 1 ms is met. if the system cannot meet this rise time specificati on, then add an external v dd brownout circuit to the rst pin of the device that holds the device in reset until v dd reaches 2.7 v and re-asserts rst if v dd drops below 2.7 v. 3. enable the on-chip v dd monitor and enable the v dd monitor as a reset source as early in code as possible. this should be the first set of instructio ns executed after the reset vector. for 'c'-based systems, this will involve modifyin g the startup code a dded by the c compiler. see your compiler documentation for more details. make certain that th ere are no delays in software between enabling the v dd monitor and enabling the v dd monitor as a reset source. code examples showing this can be found in ?an201: writing to flash from firmware", available from th e silicon laboratories web site. 4. as an added precaution, explicitly enable the v dd monitor and enable the v dd monitor as a reset source inside the functions that write and erase flash memory. the v dd monitor enable instructions should be placed just after the in struction to set pswe to a 1, but before the flash write or erase operation instruction. 5. make certain that all writes to the rstsrc (reset sources) register use di rect assignment operators and explicitly do not use the bit-wise opera tors (such as and or or). for example, "rstsrc = 0x02" is correct. "rstsrc |= 0x02" is incorrect. 6. make certain that all writes to th e rstsrc register explicitly set the porsf bit to a '1'. areas to check are initialization code which enab les other reset sources, such as the missing clock detector or comparator, for example, and instructions which force a software reset. a global search on "rstsrc" can quickly verify this. 21.4.2. pswe maintenance 7. reduce the number of places in code where the pswe bit (b0 in psctl) is set to a '1'. there should be exactly one routine in code that sets pswe to a '1' to write flash bytes and one routine in code that sets pswe and psee both to a '1' to erase flash pages. 8. minimize the number of variable accesses while psw e is set to a '1'. handle pointer address updates and loop variable maintenance outside the "pswe = 1;... pswe = 0;" area. code examples showing this can be found in ?an201: writing to flash from firmware", available from the silicon laboratories web site. 9. disable interrupts prior to setting pswe to a '1' and leave them disabled until after pswe has been reset to 0. any inte rrupts posted during the flash write or er ase operation will be serviced in priority order after the flash operation has been completed a nd interrupts have been re-enabled by software. 10.make certain that the flash write and erase poin ter variables are not located in xram. see your compiler documentation for instructions regarding how to explicitly locate variab les in different memory areas. 11. add address bounds checking to th e routines that write or erase flas h memory to ensure that a routine called with an illegal address does not result in modification of the flash. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 134 preliminary rev. 0.71 21.4.3. system clock 12.if operating from an external crystal, be advised th at crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. if the system is operating in an electrically noisy environment, use the internal oscillator or use an external cmos clock. 13.if operating from the external oscillator, switch to the internal oscillator du ring flash write or erase operations. the external oscillator can continue to run, and the cpu can switch back to the external oscillator after the flash operation has completed. additional flash recommendations and example code ca n be found in ?an201: writing to flash from firm- ware", available from the s ilicon laboratories web site. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 135 c8051f39x/37x sfr address = 0x8f; sfr page = all pages sfr definition 21.1. psctl: program store r/w control bit76543210 name psee pswe type rrrrrrr/wr/w reset 00000000 bit name function 7:2 unused read = 000000b, write = don?t care. 1psee program store erase enable setting this bit (in combination with pswe) allows an entire page of flash program memory to be erased. if this bit is logic 1 and flash writes are enabled (pswe is logic 1), a write to flash mem- ory using the movx instruction will erase the entire page that con- tains the location addressed by the movx instruction. the value of the data byte written does not matter. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. 0pswe program store write enable setting this bit allows writing a byte of data to the flash program memory using the movx write instruction. the flash location should be erased before writing data. 0: writes to flash program memory disabled. 1: writes to flash program memory enabled; the movx write instruction targets flash memory. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 136 preliminary rev. 0.71 sfr address = 0xb7; sfr page = all pages sfr definition 21.2. flk ey: flash lock and key bit76543210 name flkey[7:0] type r/w reset 00000000 bit name function 7:0 flkey[7:0] flash lock and key register. write: this register provides a lock a nd key function for flash erasures and writes. flash writes and erases are enabled by writing 0xa5 followed by 0xf1 to the flkey re gister. flash writes and erases are automatically disabled after the next write or erase is com- plete. if any wr ites to flkey are performe d incorrectly, or if a flash write or erase operation is attempted while these opera- tions are disabled, the flash will be permanently locked from writes or erasures until the next device reset. if an application never writes to flash, it can inte ntionally lock the flash by writing a non-0xa5 value to flkey from software. read: when read, bits 1?0 indicate the current flash lock state. 00: flash is write/erase locked. 01: the first key code has been written (0xa5). 10: flash is unlocked (writes/erases allowed). 11: flash writes/erases disa bled until the next reset. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 137 c8051f39x/37x sfr address = 0xb6; sfr page = all pages sfr definition 21.3. flscl: flash scale bit76543210 name fose flrt type r/w r/w r/w r/w r/w r/w r/w r/w reset 10000000 bit name function 7fose flash one-shot enable this bit enables the flash read one-shot (recommended). if the flash one-shot is disabled, th e flash sense amps are enabled for a full clock cycle during flash reads, increasing the device power consumption. 0: flash one-shot disabled. 1: flash one-shot enabled. 6:5 reserved must write 00b. 4flrt flash read timing this bit should be programmed to the smallest allowed value, according to the system clock speed. 0: sysclk < 25 mhz. 1: sysclk < 50 mhz. 3:0 reserved must write 0000b. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 138 preliminary rev. 0.71 22. eeprom (c8051f37x) the c8051f37x de vices contain 512 bytes of byte-progr ammable eeprom. the eeprom is accessible by a 2-wire bus, availabl e on eesda and eescl pins, which corresp ond to p2.2 and p2.3 respectively. the eeprom operates as a slave. the master can be either the smbus1 peripheral of the c8051f37x, internally connected to ees da and eescl, or an external master connected externally to the eesda and eescl pins. 22.1. eeprom communication protocol communication between the master and the eeprom co nsists of two types of operations: writes and reads. an overview of both operations is as follows: ? the master generates the clock on eescl. ? communication begins when the master generates a start condition by causing a falling edge in eesda when eescl is logic high. ? the master sends the slave address byte. see section 22.1.1. ? the eeprom acknowledges the receipt of the slav e address byte generating an ac k. see section 22.1.2. ? the master performs a read or writ e operation based on the setting of the r/w bit in the slave address byte. see section 22.2 and section 22.3. ? throughout communication, the stat e of eesda represents one bit of valid data when eescl is logic high: ?? the master is permitted to change the state of eesda when eescl is logic high only to generate a start or stop condition. any changes in the eesda line while the eescl line is logic high will be interpreted as a start or stop condition by the eeprom. ?? the master or eeprom is permitted to change the state of eesda when eescl is logic low. ? communication terminates when the master generate s a stop condition by causing a rising edge in eesda when eescl is logic high. ? if necessary, the master can reset the communication with the eeprom. see section 22.1.4. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 139 c8051f39x/37x 22.1.1. slave address byte the master begins a transmission by sending a start condition followed by the slave address byte (sab). slave address byte (sab) definition figure 22.1. slave address byte definition 22.1.2. acknowledgement (ack) during an acknowledgement (ack), the master or eeprom forces t he eesda line to a logic low when eescl is logic high. 22.1.3. not-ackno wledgement (nack) during a not-acknowledgement (n ack), the master or eeprom allo ws the eesda line to be pulled up to a logic high when eescl is logic high. 22.1.4. reset the eeprom can be reset in case th e smbus communication is accidenta lly interrupted (e .g. power loss) or needs to be terminated mid-stream. the reset is initialized when the master device creates a start condition. to do this, it may be necessary for the master device to monitor eesda up to nine times while cycling the eescl signal. during this process, the master checks for a logic hi gh on eesda for each rising edge of eescl. bit765432 1 0 name sla addr msb r/w value 101000variesvaries bit name function 7:2 sla slave address of eeprom. always 101000b. 1 addr msb most significant addressing bit. this bit is concatenated to the 8-bit addr ess counter to create a 9-bit address used by eeprom read and write operations. 0: address locations 0x000 to 0x0ff ar e targeted by the eeprom operations. 1: address locations 0x100 to 0x1ff ar e targeted by the eeprom operations. 0r/w eeprom read/write direction bit. instructs the eeprom to perf orm a read or write operation 0: perform an eeprom write operation 1: perform an eeprom read operation www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 140 preliminary rev. 0.71 22.2. write operation up to sixteen successive bytes may be written to the eeprom within a si ngle write operation. to write to the eeprom: 1. the master sends the start condition and the sl ave address byte with the r/w bit cleared to 0. 2. the eeprom generates an ack. 3. the master sends the write address location (a[7:0]) to the eeprom. 4. the eeprom stores the addres s location in its address co unter and generates an ack. 5. the master transmits the data byte (d[7:0]) to the eeprom. 6. the eeprom increments four leas t significant bits of the addre ss counter and generates an ack. 7. the master can repeat steps 5 and 6 up to fifteen more times. 8. the master generates a stop condition. 9. the eeprom begins its in ternal programming cycle. 10.the master transmits a start condition an d slave address with the r/w bit cleared to 0: a. if the eeprom does not generate an ack, repeat steps 8 and 9. b. if the eeprom does generate an d ack, the eeprom internal programming cycle is complete. note: if the master transmits more than sixteen bytes prior to issuing a stop condition, the last for bits of the address counter will roll over and the previous ly written data will be overwritten. figure 22.2. write operation (single byte) figure 22.3. write operation (multiple bytes) ack slave address byte (sab[7:0]) eescl eesda master sla[5:0] start data byte (d[7:0]) ack ack stop a[8] w address byte (a[7:0]) master slave slave master slave master ack ack stop data byte n + 2 (d[7:0]) slave address byte (sab[7:0]) eescl eesda master slave ack start address byte (a[7:0]) ack data byte n (d[7:0]) ack data byte n + 1 (d[7:0]) ack master slave master master data byte n + m, m < 255 (d[7:0]) master slave master slave slave slave master www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 141 c8051f39x/37x 22.3. read operation there are two oper ations to read the eeprom: current address read and se lective address read. both read operations can read up to 256 bytes within a single read operation. 22.3.1. current address read a current address read ac cesses the data at the eeprom internal address co unter?s current location. the address counter in the eeprom maintains the add ress of the last byte accessed, incremented by one. for example, if the previous operation was a re ad or write operation addressed to address location n, the internal address counter automatically increments to address n+1. to perform a current address read operation: 1. the master sends the start condition and the slave address byte with the r/w bit set to 1. 2. the eeprom generates an ack and transmits the byte of data (d[7:0]) stored at the address specified by the address counter. this a ddress will be the address from th e last read or write operation incremented by one. 3. the eeprom increments the inte rnal address co unter by one. 4. (optional) to read additional bytes: a. the master generates an ack. b. the eeprom transmits the byte of data stored at the address sp ecified by the address counter. c. the eeprom increments the in ternal address counter by one. d. repeat step 4a through 4c until the master is done reading bytes. 5. the master generates a nack. 6. the master generates a stop condition. 7. the eeprom terminate s the transmission. note: if the previous operation targeted the last byte of the eeprom, the eeprom w ill transmit the data from address location 0x00 for a current address read operation. figure 22.4. current address read operation (single byte) slave address byte (sab[7:0]) eescl eesda master sla[5:0] start data byte (d[7:0]) ack nack stop slave master a[8] r www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 142 preliminary rev. 0.71 figure 22.5. current address read operation (multiple bytes) slave address byte (sab[7:0]) eescl eesda master slave ack start data byte n (d[7:0]) ack data byte n + 1 (d[7:0]) ack data byte n + m, m < 255 (d[7:0]) nack stop master slave master slave master www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 143 c8051f39x/37x 22.3.2. selective address read in a selective address read operation, the master selects the target memory location for the read operation. to perform a selective address read: 1. the master sends the start condition and the slave address byte with the r/w bit set to 1. 2. the eeprom generates an ack. 3. the master sends the read memory address (a [7:0]) to the eeprom. 4. the eeprom stores the address in the address counter and generates an ack. 5. the master again sends the slave ad dress byte with the r/w bit set to 1. 6. the eeprom generates an ack. 7. the eeprom sends the byte of data (d[7 :0]) specified by the address counter. 8. the eeprom increments the inte rnal address co unter by one. 9. (optional) to read additional bytes: a. the master generates an ack. b. the eeprom sends the byte of data (d[7 :0]) specified by the address counter. c. the eeprom increments the in ternal address counter by one. d. repeat steps9a through 9c until the master reads all of the desired bytes. 10.the master generates a nack. 11. the master generates a stop condition. 12.the eeprom terminate s the transmission. note: if the selective read operation overflows the top of memory, the eeprom address counter will wrap, and the eeprom transmit the data from address location 0x00. figure 22.6. selective address read (single byte) slave address byte (sab[7:0]) eescl eesda master slave ack start address byte (a[7:0]) ack slave address byte (sab[7:0]) ack data byte (d[7:0]) nack stop master slave master master slave www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 144 preliminary rev. 0.71 figure 22.7. selective address read (multiple bytes) nack ack stop data byte n + 1 (d[7:0]) slave address byte (sab[7:0]) eescl eesda master slave ack start address byte (a[7:0]) ack slave address byte (sab[7:0]) ack data byte n (d[7:0]) ack master slave master master slave data byte n + m, m < 255 (d[7:0]) slave master slave master www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 145 c8051f39x/37x 23. cyclic redundancy check unit (crc0) c8051f39x/37x devices include a cyclic redundancy check unit (crc0) that can perform a crc using a 16-bit polynomial. crc0 accepts a stream of 8-bit dat a written to the crc0in register. crc0 posts the 16- bit result to an internal register. the internal result register may be accessed indirectly using the crc0pnt bits and crc0dat register, as shown in figure 23.1. crc0 also has a bit reverse register for quick data manipulation. figure 23.1. crc0 block diagram 23.1. crc algorithm the c8051f39x/37x crc unit generates a crc resu lt equivalent to the following algorithm: 1. xor the input with the most-significant bits of the cu rrent crc result. if this is the first iteration of the crc unit, the current crc result will be the set initial value (0x00000000 or 0xffffffff). 2a. if the msb of the crc result is set, shift the crc result and xor the re sult with the selected polynomial. 2b. if the msb of the crc result is not set, shift the crc result. repeat steps 2a/2b for the number of input bits (8). the algorithm is also described in the following exam- ple. crc0in autoen crc0dat crc engine crc0flip write crc0auto flash memory automatic crc controller crc0st[0] crc0st[1] crc0st[2] crc0st[3] crc0st[4] crc0st[5] crc0done crc0cnt crc0cnt[0] crc0cnt[1] crc0cnt[2] crc0cnt[3] crc0cnt[4] crc0cn crc0val crc0init crc0pnt crc0flip read 2 to 1 mux result 16 8 88 8 8 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 146 preliminary rev. 0.71 the 16-bit c8051f39x/37x crc algorithm can be described by the following code: unsigned short updatecrc (unsigned short crc_acc, unsigned char crc_input) { unsigned char i; // loop counter #define poly 0x1021 // create the crc "dividend" for polynomial arithmetic (binary arithmetic // with no carries) crc_acc = crc_acc ^ (crc_input << 8); // "divide" the poly into the dividend using crc xor subtraction // crc_acc holds the "remainder" of each divide // // only complete this division for 8 bits since input is 1 byte for (i = 0; i < 8; i++) { // check if the msb is set (if msb is 1, then the poly can "divide" // into the "dividend") if ((crc_acc & 0x8000) == 0x8000) { // if so, shift the crc value, and xor "subtract" the poly crc_acc = crc_acc << 1; crc_acc ^= poly; } else { // if not, just shift the crc value crc_acc = crc_acc << 1; } } // return the final remainder (crc value) return crc_acc; } table 23.1 lists several input valu es and the associated outputs usi ng the 16-bit c8051f39x/37x crc algorithm: table 23.1. example 16-bit crc outputs input output 0x63 0xbd35 0x8c 0xb1f4 0x7d 0x4eca 0xaa, 0xbb, 0xcc 0x6cf6 0x00, 0x00, 0xaa, 0xbb, 0xcc 0xb166 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 147 c8051f39x/37x 23.2. preparing fo r a crc calculation to prepare crc0 for a crc calculation, software should set the initial value of the result. the polynomial used for the crc computation is 0x1021. the crc0 resu lt may be initialized to one of two values: 0x0000 or 0xffff. the following steps can be used to initialize crc0. 1. select the initial result value (set crc0val to 0 for 0x00 00 or 1 for 0xffff). 2. set the result to its initia l value (write 1 to crc0init). 23.3. performing a crc calculation once crc0 is initialized, the input data stream is sequenti ally written to crc0in, one byte at a time. the crc0 result is automatically updated after each byte is written. the crc engine may also be configured to automatically perform a crc on one or more 256 byte blocks read from flash. the following steps can be used to automatically perform a crc on flash memory. 1. prepare crc0 for a crc calculation as shown above. 2. write the index of the starting page to crc0auto. 3. set the autoen bit to 1 in crc0auto. 4. write the number of 256 byte blocks to perform in the crc calculation to crc0cnt. 5. write any value to crc0cn (or or its contents with 0x00) to initiate the c rc calculation. the cpu will not execute code any additional code until the crc operation completes. see the note in sfr definition 23.1. crc0cn: crc0 cont rol for more information on how to properly initiate a crc calculation. 6. clear the autoen bit in crc0auto. 7. read the crc result using the procedure below. 23.4. accessing th e crc0 result the internal crc0 result is 16 bits. the crc0pnt bits select the byte that is ta rgeted by r ead and write operations on crc0dat and increment after each read or write. the ca lculation result will remain in the internal cr0 result register until it is set, overwritten, or addi tional data is written to crc0in. 23.5. crc0 bit reverse feature crc0 includes hardware to reverse the bit order of eac h bit in a byte as shown in figure 23.2. each byte of data written to crc0flip is read back bit reversed. for example, if 0xc0 is written to crc0flip, the data read back is 0x03. bit reversal is a useful mathem atical function used in algorithms such as the fft. figure 23.2. bit reverse register crc0flip write crc0flip read www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 148 preliminary rev. 0.71 sfr address = 0xdf; sfr page = all pages sfr definition 23.1. crc0cn: crc0 control bit76543210 name crc0init crc0val crc0pnt type rrrrr/wr/wrr/w reset 00010000 bit name function 7:4 unused read = 0001b; write = don?t care. 3crc0init crc0 result initialization bit. writing a 1 to this bit initializ es the entire crc result based on crc0val. 2crc0val crc0 set value initialization bit. this bit selects the set value of the crc result. 0: crc result is set to 0x00000000 on write of 1 to crc0init. 1: crc result is set to 0xffffffff on write of 1 to crc0init. 1 unused read = 0b; write = don?t care. 0 crc0pnt crc0 result pointer. specifies the byte of the crc result to be read/written on the next access to crc0dat. the value of these bits will auto-increment upon each read or write. 0: crc0dat accesses bits 7?0 of the 16-bit crc result. 1: crc0dat accesses bits 15?8 of the 16-bit crc result. note: upon initiation of an automatic crc calculation, the three cycles following a write to crc0cn that initiate a crc operation must only contain instructions which exec ute in the same number of cycles as the number of bytes in the instruction. an example of such an instruction is a 3-byte mov that targets the crc0flip register. when programming in c, the dummy value wr itten to crc0flip should be a non-zero value to prevent the compiler from generating a 2-byte mov instruction. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 149 c8051f39x/37x sfr address = 0x9c; sfr page = all pages sfr address = 0x9e; sfr page = all pages sfr definition 23.2. crc0in: crc0 data input bit76543210 name crc0in[7:0] type r/w reset 00000000 bit name function 7:0 crc0in[7:0] crc0 data input. each write to crc0in results in the written data being com- puted into the existing crc result according to the crc algorithm described in section 23.1 sfr definition 23.3. crc0dat: crc0 data output bit76543210 name crc0dat[7:0] type r/w reset 00000000 bit name function 7:0 crc0dat[7:0] crc0 data output. each read or write performed on crc0dat targets the crc result bits pointed to by the crc0 result pointer (crc0pnt bits in crc0cn). www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 150 preliminary rev. 0.71 sfr address = 0xdd; sfr page = all pages sfr definition 23.4. crc0auto: crc0 automatic control bit7 6 543210 name autoen crc0st[5:0] type r/w r/w r/w reset 0 0 000000 bit name function 7autoen automatic crc calc ulation enable. when autoen is set to 1, any write to crc0cn will initi- ate an automatic crc starting at flash sector crc0st and continuing for crc0cnt sectors. 6 reserved must write 0b. 5:0 crc0st[5:0] automatic crc calculat ion starting block. these bits specify the flash block to start the automatic crc calculation. the starting address of the first flash block included in the automatic crc calculation is crc0st x block size. note: the block size is 256 bytes. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 151 c8051f39x/37x sfr address = 0xde; sfr page = all pages sfr definition 23.5. crc0cnt: crc0 automatic flash sector count bit7 6543210 name crcdone crc0cnt[4:0] type rr/w r/w reset 1 0000000 bit name function 7 crcdone crcdone automatic crc calculation complete. set to 0 when a crc calculation is in progress. code exe- cution is stopped during a crc calculation; therefore, reads from firmware will always return 1. 6:5 reserved must write 00b. 4:0 crc0cnt[4:0] automatic crc calcul ation block count. these bits specify the number of flash blocks to include in an automatic crc calculation. the last address of the last flash block included in the automatic crc calculation is (crc0st+crc0cnt) x block size - 1. notes: 1. the block size is 256 bytes. 2. the maximum number of blo cks that may be computed in a single operation is 31. to compute a crc on all 32 blocks, perform one operation on 31 blocks, then perform a second operation on 1 block without clearing the crc result. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 152 preliminary rev. 0.71 sfr address = 0x9a; sfr page = all pages sfr definition 23.6. crc 0flip: crc0 bit flip bit76543210 name crc0flip[7:0] type r/w reset 00000000 bit name function 7:0 crc0flip[7:0] crc0 bit flip. any byte written to crc0flip is read back in a bit- reversed order, i.e., the written lsb becomes the msb. for example: if 0xc0 is written to crc0f lip, the data read back will be 0x03. if 0x05 is written to crc0fl ip, the data read back will be 0xa0. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 153 c8051f39x/37x 24. reset sources reset circuitry allows the controller to be easily plac ed in a predefined default condition. upon entering this reset state, the following events occur: ? cip-51 halts program execution ? special function registers (sfrs) are initialized to their defined reset values ? external port pins are forced to a known state ? interrupts and timers are disabled. all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal data memory are unaffected during a reset; any prev iously stored data is preserved. however, since the stack pointer sfr is reset, the stack is effectively lo st, even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones) in open-drain mode. weak pullups are enabled dur- ing and after the reset. for v dd monitor and power-on resets, the rst pin is driven low until the device exits the reset state. on exit from the reset state, the program counter (pc) is reset, and the system clock defaults to the inter- nal oscillator. the watchdog timer is enabled with the system clock divided by 12 as its clock source. pro- gram execution begins at location 0x0000. figure 24.1. reset sources pca wdt missing clock detector (one- shot) (software reset) system reset reset funnel px.x px.x en swrsf system clock cip-51 microcontroller core extended interrupt handler en wdt enable mcd enable errant flash operation /rst (wired-or) power on reset '0' + - comparator 0 c0rsef vdd + - supply monitor enable www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 154 preliminary rev. 0.71 24.1. power-on reset during power-up, the device is held in a reset state and the rst pin is driven low until v dd settles above v rst . a delay occurs before the device is released from reset; the delay decreases as the v dd ramp time increases (v dd ramp time is defined as how fast v dd ramps from 0 v to v rst ). figure 24.2. plots the power-on and v dd monitor reset timing. the maximum v dd ramp time is 1 ms; slower ramp times may cause the device to be released from reset before v dd reaches the v rst level. for ramp times less than 1 ms, the power-on reset delay (t pordelay ) is typically less than 0.3 ms. on exit from a power-on reset, the porsf flag (rst src.1) is set by hardware to logic 1. when porsf is set, all of the other reset flags in the rstsrc regist er are indeterminate (porsf is cleared by all other resets). since all resets cause program execution to begin at the same location (0x0000) software can read the porsf flag to determine if a power-up was t he cause of reset. the content of internal data mem- ory should be assumed to be undefined after a power-on reset. the v dd monitor is enabled following a power-on reset. figure 24.2. power-on and v dd monitor reset timing power-on reset vdd monitor reset /rst t volts 1.0 2.0 logic high logic low t pordelay v d d 2.70 2.55 v rst vdd www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 155 c8051f39x/37x 24.2. power-fail reset / v dd monitor when a power-down transition or power irregularity causes v dd to drop below v rst , the power supply monitor will drive the rst pin low and hold the cip-51 in a reset state (see figure 24.2). when v dd returns to a level above v rst , the cip-51 will be released from the reset st ate. note that even though internal data memory contents are not altered by the power-fa il reset, it is impossib le to determine if v dd dropped below the level required for data retention. if the porsf flag reads ?1?, the data may no longer be valid. the v dd monitor is enabled after power-on resets. its defined state (enabled/disabled) is not altered by any other reset source. for example, if the v dd monitor is disabled by code and a software reset is performed, the v dd monitor will still be disabled after the reset. important note: if the v dd monitor is being turned on from a disabled state, it should be enabled before it is selected as a reset source. selecting the v dd monitor as a reset source before it is enabled and stabi- lized may cause a system reset. in some applications, this reset may be undesirable. if this is not desirable in the application, a delay should be introduced betwe en enabling the monitor and selecting it as a reset source. the procedure for enabling the v dd monitor and configuring it as a reset source from a disabled state is shown below: 1. enable the v dd monitor (vdmen bit in vdm0cn = ?1?). 2. if necessary, wait for the v dd monitor to stabilize. 3. select the v dd monitor as a reset source (porsf bit in rstsrc = ?1?). see figure 24.2 for v dd monitor timing; note that the power-on -reset delay is not incurred after a v dd monitor reset. see section ?7. electri cal characteristics? on page 32 for complete electrical characteristics of the v dd monitor. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 156 preliminary rev. 0.71 sfr address = 0xff; sfr page = all pages sfr definition 24.1. vdm0cn: v dd monitor control bit7654321 0 name vdmen vddstat vdmlvl type r/w r r/w r r r r r reset varies varies 0 0 0 0 0 0 bit name function 7vdmen v dd monitor enable. this bit turns the v dd monitor circuit on/off. the v dd monitor cannot generate system resets until it is also selected as a reset source in register rstsrc (sfr definition 24.2). selecting the v dd monitor as a reset source before it has stabilized may generate a system reset. in systems where this reset would be undesirable, a delay should be intro- duced between enabling the v dd monitor and selecting it as a reset source. 0: v dd monitor disabled. 1: v dd monitor enabled. 6 vddstat v dd status. this bit indicates the current power supply status (v dd mon- itor output). 0: v dd is at or below the v dd monitor threshold. 1: v dd is above the v dd monitor threshold. 5vdmlvl vdd monitor level select. 0: vdd monitor threshold is set to vrst-low. 1: vdd monitor threshold is set to vrst-high. this setting is required for any system wit h firmware that writes and/or erases flash. 4:0 unused read = 000000b; write = don?t care. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 157 c8051f39x/37x 24.3. external reset the external rst pin provides a means for external circuitry to force the device into a reset state. assert- ing an active-low signal on the rst pin generates a reset; an external pullup and/or decoupling of the rst pin may be necessary to avoid erroneous noise-induce d resets. see section ?7. e lectrical characteristics? on page 32 for complete rst pin specifications. the pinrsf flag (rstsr c.0) is set on exit from an exter- nal reset. 24.4. missing cl ock detector reset the missing clock detector (mcd) is a one-shot circuit th at is triggered by the system clock. if the system clock remains high or low for more than 100 s, the one-shot will time ou t and generate a reset. after a mcd reset, the mcdrsf flag (rstsrc.2) will read ?1 ?, signifying the mcd as th e reset source; otherwise, this bit reads ?0?. writing a ?1? to the mcdrsf bit enables the missing clock detector; writing a ?0? disables it. the state of the rst pin is unaffected by this reset. 24.5. comparator0 reset comparator0 can be configured as a reset source by writing a ?1? to the c0rsef flag (rstsrc.5). comparator0 should be enabled and allowed to settle prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted rese t. the comparator0 reset is active-low: if the non- inverting input voltage (on cp0+) is less than the inverting input voltage (on cp0-), the device is put into the reset state. af ter a comparator0 reset, t he c0rsef flag (rstsrc.5) will read ?1? signifying comparator0 as the reset source; otherwise, this bit reads ?0?. the state of the rst pin is unaffected by this reset. 24.6. pca watchdog timer reset the programmable watchdog timer (wdt) function of the programmable counter array (pca) can be used to prevent software from running out of cont rol during a system malfunction. the pca wdt function can be enabled or disabled by software as de scribed in section ?32.4. watchdog timer mode? on page 284; the wdt is enabled and clocked by sysclk / 12 following any reset. if a system malfunction prevents user software from updating the wdt, a re set is generated and the wdtrsf bit (rstsrc.5) is set to ?1?. the state of the rst pin is unaffected by this reset. 24.7. flash error reset if a flash read/write/e rase or program read target s an illegal address, a system reset is generated. this may occur due to any of the following: ? a flash write or erase is attempted above user code space. this occurs when pswe is set to ?1? and a movx write operation targets an address above address 0x3dff. ? a flash read is attempted above user code space. this occurs when a movc operation targets an address above address 0x3dff. ? a program read is attempted above user code space. this occurs when user code attempts to branch to an address above 0x3dff. ? a flash read, write or erase attempt is restrict ed due to a flash security setting (see section ?21.3. security options? on page 131). the ferror bit (rstsrc.6) is set following a flash error reset. the state of the rst pin is unaffected by this reset. 24.8. software reset software may force a reset by writ ing a ?1? to the swrsf bit (rstsrc.4). the swrsf bit will read ?1? fol- lowing a software forced reset. the state of the rst pin is unaffected by this reset. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 158 preliminary rev. 0.71 sfr address = 0xef; sfr page = all pages sfr definition 24.2. r stsrc: reset source bit76543210 name ferror c0rsef swrsf wdtrsf mcdrsf porsf pinrsf type r r r/w r/w r r/w r/w r reset 0 varies varies varies var ies varies varies varies bit name description write read 7 unused unused. don?t care. 0 6ferror flash error reset flag. n/a set to ?1? if flash read/ write/erase error caused the last reset. 5 c0rsef comparator0 reset enable and flag. writing a ?1? enables comparator0 as a reset source (active-low). set to ?1? if comparator0 caused the last reset. 4swrsf software reset force and flag. writing a ?1? forces a sys- tem reset. set to ?1? if last reset was caused by a write to swrsf. 3 wdtrsf watchdog timer reset flag. n/a set to ?1? if watchdog timer overflow caused the last reset. 2 mcdrsf missing clock detector enable and flag. writing a ?1? enables the missing clock detector. the mcd triggers a reset if a missing clock condition is detected. set to ?1? if missing clock detector timeout caused the last reset. 1porsf power-on / v dd monitor reset flag, and v dd monitor reset enable. writing a ?1? enables the v dd monitor as a reset source. writing ?1? to this bit before the v dd monitor is enabled and stabilized may cause a system reset. set to ?1? anytime a power- on or v dd monitor reset occurs. when set to ?1? all other rstsrc flags are inde- terminate. 0pinrsf hw pin reset flag. n/a set to ?1? if rst pin caused the last reset. note: do not use read-modify-write operations on this register www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 159 c8051f39x/37x 25. power management modes the c8051f39x/37x devices have three software programmable power management modes: idle, stop, and suspend. idle mode and stop mode are part of t he standard 8051 architecture, while suspend mode is an enhanced power-saving mode implemented by the high-speed oscillator. idle mode halts the cpu while leaving the peripherals and clocks active. in stop mode, the cpu is halted, all interrupts and timers (except the missing clock de tector) are inactive, and the internal oscillator is stopped (analog peripherals remain in their se lected states; the external o scillator is not affected). sus- pend mode is similar to stop mode in that the internal oscillator an d cpu are halted, but the device can wake on events such as a port mismatch, comparator low output, or a timer 3 overflow. since clocks are running in idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering idle. stop mode and suspend mode consume the least power because the majority of the device is shut down with no clocks active. sfr definition 25.1 describes the power control register (pcon) used to control the c8051f39x/37x's stop and idle power manage- ment modes. suspend mode is cont rolled by the suspend bit in the oscicn register (sfr definition 26.3). although the c8051f39x/37x has idle, stop, and sus pend modes available, more control over the device power can be achieved by enabling/disabling individ ual peripherals as needed. each analog peripheral can be disabled when not in use and placed in low power mode. digital peripherals, such as timers or serial buses, draw little power when they are not in use. turning off oscillators lowers power consumption considerably, at the expense of reduced functionality. 25.1. idle mode setting the idle mode select bit (pcon.0) causes th e hardware to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes execution. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle mode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pen ding interrupt will be serviced and the next in struction to be executed after the return from interrupt (reti) will be the instruction imme diately following the one that set the idle mode select bit. if idle mode is termin ated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. note: if the instruction following the write of the idle bit is a single-byte instruction and an interrupt occurs during the execution phase of the instruction that sets the idle bit, the cpu may not wake from idle mode when a future interrupt occurs. therefore, instructions that set the idle bit should be followed by an instruction that has two or more opcode bytes, for example: // in ?c?: pcon |= 0x01; // set idle bit pcon = pcon; // ... followed by a 3-cycle dummy instruction ; in assembly: orl pcon, #01h ; set idle bit mov pcon, pcon ; ... followed by a 3-cycle dummy instruction if enabled, the watchdog timer (wdt) will eventually cause an internal watchdog reset a nd thereby termi- nate the idle mode. this feature pr otects the system from an unintended permanent shutdown in the event of an inadvertent write to the pcon register. if this behavior is not desired, the wdt may be disabled by software prior to entering the idle mo de if the wdt was initially configured to allow this operation. this pro- vides the opportunity for additional power savings, allo wing the system to remain in the idle mode indefi- nitely, waiting for an external stim ulus to wake up the system. refer to section ?24.6. pca watchdog timer reset? on page 157 for more information on the use a nd configuration of the wdt. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 160 preliminary rev. 0.71 25.2. stop mode setting the stop mode select bit (pcon.1) causes the co ntroller core to enter stop mode as soon as the instruction that sets the bit completes execution. before entering stop mode, the system clock must be sourced by the internal high -frequency oscillator. in st op mode the internal oscilla tor, cpu, and all digital peripherals are stopp ed; the state of the external oscillator circ uit is not affected. ea ch analog peripheral (including the external oscillator circuit) may be shut down individually prior to entering stop mode. stop mode can only be terminated by an internal or external reset. on reset, the device performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detector will cause an inte rnal reset and thereby te rminate the stop mode. the missing clock detector should be disabled if the cpu is to be put to in stop mode for longer than the mcd timeout. by default, when in stop mode the internal regulator is still active. ho wever, the regulator can be config- ured to shut down while in stop mode to save pow er. to shut down the regulator in stop mode, the stopcf bit in register reg01cn should be set to 1 prior to setting the stop bit (see sfr definition 25.1). if the regulator is shut down using the stopcf bit, only the rst pin or a full power cycle are capa- ble of resetting the device. 25.3. suspend mode setting the suspend bit (oscicn.5) causes the hardware to halt the cpu and the high-frequency inter- nal oscillator, and go into suspend mode as soon as the instruction that sets the bit completes execution. all internal registers and memory main tain their original data. most digita l peripherals are not active in sus- pend mode. the exception to this is the port match feature and timer 3, when it is run from an external oscillator source or the inte rnal low-frequency oscillator. suspend mode can be terminated by four types of ev ents, a port match (described in section ?27.5. port match? on page 181), a timer 3 overflow (described in section ?31.3. timer 3? on page 257), a comparator low output (if enabled), or a device reset event. note that in order to run timer 3 in suspend mode, the timer must be configured to clock fr om either the external clock source or the internal low-frequency oscil- lator source. when suspend mode is terminated, the device will continue execution on the instruction fol- lowing the one that set the suspend bit. if the wake event (port match or timer 3 overflow) was configured to gener ate an interrupt, the interrup t will be serviced upon waking the device. if suspend mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 161 c8051f39x/37x sfr address = 0x87; sfr page = all pages sfr definition 25.1. pcon: power control bit76543210 name gf[5:0] stop idle type r/w r/w r/w reset 00000000 bit name function 7:2 gf[5:0] general purpose flags 5?0. these are general purpose flags for use under software control. 1stop stop mode select. setting this bit will place the cip- 51 in stop mode. this bit will always be read as 0. 1: cpu goes into st op mode (internal oscillator stopped). 0idle idle: idle mode select. setting this bit will place the cip-51 in idle mode. this bit will always be read as 0. 1: cpu goes into idle mode. (shuts off clock to cpu, but clock to timers, interrupts, serial ports, and analog peripherals are still active.) www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 162 preliminary rev. 0.71 26. oscillators and clock selection c8051f39x/37x devices incl ude a programmable internal high-frequency oscillato r, a programmable inter- nal low-frequency oscillator, an internal low-power oscillator, and an external oscillator drive circuit. the internal high-frequency oscillator can be enabled/disabled and calibrated using the oscicn and oscicl registers, as shown in figure 26.1. the internal low-frequency oscillato r can be enabled/disabled and cali- brated using the osclcn register. the internal low-power oscillator is automatica lly enabled and disabled when selected and deselected as the system clock. the system clock can be sourced by the external oscil- lator circuit or any internal oscilla tor. the internal high- frequency and lo w-frequency oscillators offer a selectable post-scaling feature. figure 26.1. oscillator options osc 49 mhz high frequency internal oscillator input circuit en sysclk oscicl oscicn ioscen ifrdy suspend stsync ifcn1 ifcn0 oscxcn xoscmd2 xoscmd1 xoscmd0 xfcn2 xfcn1 xfcn0 osclcn osclen osclrdy osclf3 osclf2 osclf1 osclf0 oscld1 oscld0 80 khz low frequency internal oscillator en 1, 2, 4, 8 oscld osclf osclf oscld osclen osclen xtal1 xtal2 option 2 vdd xtal2 option 1 10m option 3 xtal2 option 4 xtal2 2, 4, 8, 16 (49 mhz) clksel clksl2 clksl1 clksl0 20 mhz low power internal oscillator (20 mhz) www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 163 c8051f39x/37x 26.1. system clock selection the clksl[2:0] bits in register cl ksel select which osc illator source is used as the system clock. clksl[2:0] must be set to 001b for t he system clock to run from the exte rnal oscillator; however the exter- nal oscillator may still clock certain per ipherals (timers, pca) when the inte rnal oscillator is selected as the system clock. the system clock may be switched on-t he-fly between any of the oscillator sour ces so long as the selected clock source is enabled and has settled. the internal high-frequency and low-frequency oscillators require little start-up time and may be selected as the system clock immediately fo llowing the register writ e which enables the oscillator. the external rc and c modes also typically require no startup time. external crystals and ceramic resonato rs however, typically require a start-up time before they are settled and ready for use. the crystal valid flag (xtlvld in re gister oscxcn) is set to '1' by hardware when the external crystal or cera mic resonator is settled. in crystal mode, to avoid reading a false xtlvld, soft- ware should delay at least 1 ms between enabling the external oscillator and checking xtlvld. sfr address = 0xa9; sfr page = all pages sfr definition 26.1. clksel: clock select bit76543210 name clksl[2:0] type rrrrr r/w reset 00000000 bit name function 7:3 unused read = 00000b; write = don?t care 2:0 clksl[2:0] system clock source select bits. 000: sysclk derived from the internal high-frequency oscilla- tor and scaled per the ifcn bits in register oscicn. 001: sysclk derived from the external oscillator circuit. 010: sysclk derived from the in ternal low-fre quency oscilla- tor and scaled per the oscld bits in register osclcn. 011: sysclk derived directly fr om the internal high-frequency oscillator. 100: reserved. 101: sysclk derived from the in ternal low-pow er oscillator. 110: reserved. 111: reserved. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 164 preliminary rev. 0.71 26.2. programmable internal high-frequency (h-f) oscillator all c8051f39x/37x devices include a programmable internal hi gh-frequency oscillator that defaults as the system clock after a system reset. th e internal oscillator period can be adjusted via the oscicl register as defined by sfr definition 26.2. on c8051f39x/37x devices, osci cl is factory calibra ted to obtain a 49 mhz base frequency. the system clock may be derived directly from the prog rammed internal oscillator, or from a divided ver- sion, with factors of 2, 4, 8, or 16, as defined by the ifcn bits in register oscicn. the divide value defaults to 16 following a reset. 26.2.1. internal os cillator suspend mode when software writes a logic 1 to suspend (oscicn.5) , the internal oscillator is suspended. if the sys- tem clock is derived from t he internal oscillator, the input clock to the peripheral or cip-51 will be stopped until one of the following events occur: ? port 0 match event. ? port 1 match event. ? comparator 0 enabled and output is logic 0. ? timer3 overflow event. when one of the oscillator awakening events occur, the internal oscillato r, cip-51, and affe cted peripherals resume normal operation, regardless of whether the event also causes an interrupt. the cpu resumes execution at the instruction fo llowing the write to suspend. sfr address = 0xb3; sfr page = all pages sfr definition 26.2. oscicl: intern al h-f oscillator calibration bit76543210 name oscicl[6:0] type rr/w reset 0 varies varies varies var ies varies varies varies bit name function 7 unused unused. read = 0; write = don?t care 6:0 oscicl[6:0] internal oscillator calibration bits. these bits determine the internal oscillator period . when set to 0000000b, the h-f oscillator oper ates at its fastest setting. when set to 1111111b, the h-f osc illator operates at its slow- est setting. the reset value is factory calibrated to generate an internal oscillator frequency of 49 mhz. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 165 c8051f39x/37x sfr address = 0xb2; sfr page = all pages sfr definition 26.3. oscicn: inte rnal h-f oscillator control bit76 5 43210 name ioscen ifrdy suspend stsync ifcn[1:0] type r/w r r/w r r r r/w reset 11 0 00000 bit name function 7ioscen internal h-f osci llator enable bit. 0: internal h-f oscillator disabled. 1: internal h-f oscillator enabled. 6 ifrdy internal h-f oscillator frequency ready flag. 0: internal h-f oscillator is not running at programmed fre- quency. 1: internal h-f oscillator is running at prog rammed frequency. 5 suspend internal oscillator suspend enable bit. setting this bit to logic 1 places the internal oscillator in sus- pend mode. the internal oscilla tor resumes operation when one of the suspend mode awakening events occurs. 4stsync suspend timer synchronization bit. this bit is used to indicate when it is safe to read and write the registers associated with the suspend wake-up timer. if a suspend wake-up source other than the timer has brought the oscillator out of suspend mode, it may take up to three timer clocks before the timer can be read or written. when stsync reads '1', reads and writes of the timer register should not be performed. when stsync reads '0', it is safe to read and write the timer registers. 3:2 unused unused. read = 00b; write = don?t care 1:0 ifcn[1:0] internal h-f oscillator frequency divider control bits. these bits control the oscillato r clock divider when the clock divider is selected as t he system clock source. 00: internal h-f divide ratio = 16. 01: internal h-f divide ratio = 8. 10: internal h-f divide ratio = 4. 11: internal h-f divide ratio = 2. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 166 preliminary rev. 0.71 26.3. programmable internal low-frequency (l-f) oscillator all c8051f39x/37x devices include a programmable low-frequency internal oscillator, which is calibrated to a nominal frequency of 80 khz. the low-frequency oscillator circui t includes a divider that can be changed to divide the clock by 1, 2, 4, or 8, using the oscld bits in the osclcn register (see sfr defi- nition 26.4). additionally, the oscl f[3:0] bits can be used to adjust the oscillator?s output frequency. 26.3.1. calibrating the internal l-f oscillator timers 2 and 3 include capture func tions that can be used to capture the oscillato r frequency, when run- ning from a known time base. when either timer 2 or timer 3 is configured fo r l-f oscillator capture mode, a falling edge (timer 2) or rising edge (timer 3) of the low-frequency osc illator?s output will cause a capture event on the corresponding timer. as a capture event occurs, the current timer value (tmrnh:tmrnl) is copied into the timer reload regi sters (tmrnrlh:tmrnrll). by recording the differ- ence between two successive time r capture values, the lo w-frequency oscillator? s period can be calcu- lated. the osclf bits can then be adjusted to produce the desire d oscillator frequency. sfr address = 0xe3; sfr page = all pages sfr definition 26.4. osclcn: inte rnal l-f oscill ator control bit76543210 name osclen osclrdy oscl f[3:0] oscld[1:0] type r/w r r.w r/w reset 0 0 varies varies varies varies 0 0 bit name function 7osclen internal l-f oscillator enable. 0: internal l-f oscillator disabled. 1: internal l-f oscillator enabled. 6osclrdy internal l-f oscillator ready. 0: internal l-f oscillato r frequency not stabilized. 1: internal l-f oscilla tor frequency stabilized. note: osclrdy is only set back to 0 in the event of a device reset or a change to the oscld[1:0] bits. 5:2 osclf[3:0] internal l-f oscillator frequency control bits. fine-tune cont rol bits for the internal l-f oscillator frequency. when set to 0000b, the l-f oscillator operates at its fastest setting. when set to 1111b, the l-f oscillator operates at its slowest setting. the osclf bits should only be changed by firmware when the l-f oscillato r is disabled (osclen = 0). 1:0 oscld[1:0] internal l-f oscillator divider select. 00: divide by 8 selected. 01: divide by 4 selected. 10: divide by 2 selected. 11: divide by 1 selected. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 167 c8051f39x/37x 26.4. internal low -power oscillator all c8051f39x/37x devices include a low-power internal os cillator with a nominal frequency of 20 mhz. the low-power oscillator is automatically enabled when selected as the system clock and disabled when not in use. see table 7.9, ?internal low-power oscilla tor electrical characteristics,? on page 37 for com- plete oscillator specifications. 26.5. external osci llator drive circuit the external oscillator circuit may drive an external cr ystal, ceramic resona tor, capacitor, or rc network. a cmos clock may also provide a clock input. figure 26.1 shows a block diagram of the four external oscil- lator options. the external oscillator is enabled a nd configured using the oscxcn register (see sfr defi- nition 26.5). important note on external oscillator usage: port pins must be configured when using the external oscillator circuit. when the external oscillator drive ci rcuit is enabled in crystal /resonator mode, port pins p0.2 and p0.3 are used as xtal1 and xtal2, respectively. when th e external oscillator drive circuit is enabled in capacitor, rc, or cmos clock mode, port pin p0.3 is used as xtal2. the port i/o crossbar should be configured to sk ip the port pin used by the oscillator ci rcuit; see section ?27.3. priority crossbar decoder? on page 176 for crossbar co nfiguration. additionally, when usin g the external oscillator circuit in crystal/resonator, capacitor, or rc mode, the associated port pins should be configured as analog inputs . in cmos clock mode, the associated pin should be configured as a digital input . see section ?27.4. port i/o initialization? on page 178 for deta ils on port inpu t mode selection. the external oscillato r output may be selected as the system clock or used to clock some of the digital peripherals (e.g. timers, pca, etc.). see the data shee t chapters for each digital peripheral for details. see section ?7. electrical characteri stics? on page 32 for comple te oscillator specifications. 26.5.1. external crystal mode if a crystal or ceramic resonator is used as the ex ternal oscillator, the cr ystal/resonator and a 10 m ?? resis- tor must be wired across the xtal1 and xtal2 pins as shown in figure 26.1, ?crystal mode?. appropriate loading capacitors should be added to xtal1 and xtal2, and both pins should be configured for analog i/ o with the digital output drivers disabled. the capacitors shown in the external crystal configur ation provide the load capacitance required by the crystal for correct oscillation. these capacitors are ?in series? as seen by the crystal and ?in parallel? with the stray capacitance of the xtal1 and xtal2 pins. note: the recommended load capacitance depends upon the crystal and the manufacturer. refer to the crystal data sheet when completing these calculations. the equation for determining the load capacitance for two capacitors is where: c a and c b are the capacitors connec ted to the crystal leads. c s is the total stray capacitance of the pcb. the stray capacitance for a typical layout where the crysta l is as close as possible to the pins is 2-5 pf per pin. if c a and c b are the same (c), then the equation becomes c l c a c b ? c a c b + -------------------- c s + = c l c 2 --- - c s + = www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 168 preliminary rev. 0.71 for example, a tuning-fork crystal of 32 khz with a recommended load capacitance of 12.5 pf should use the configuration shown in figure 26.1, option 1. with a stray capacitance of 3 pf per pin (6 pf total), the 13 pf capacitors yield an equivalent capacitance of 12.5 pf across the crystal, as shown in figure 26.2. figure 26.2. external crystal example important note on external crystals: crystal oscillator circuits are qui te sensitive to pcb layout. the crystal should be placed as close as possible to th e xtal pins on the device. the traces should be as short as possible and shielded with ground plane fr om any other traces whic h could introduce noise or interference. when using an external crystal, the external oscillator drive circuit must be configured by software for crys- tal oscillator mode or crystal oscillator mode with divide by 2 stage . the divide by 2 stage ensures that the clock derived from the external o scillator has a duty cycle of 50%. t he external oscillator frequency con- trol value (xfcn) must also be specified based on the crystal frequency (see sfr definition 26.5). when the crystal oscillator is first enabled, the external osc illator valid detector allo ws software to deter- mine when the external system clock is valid and running. sw itching to the external oscilla tor before the crystal oscillator has stabilized can re sult in unpredictable behavior. th e recommended procedure for start- ing the crystal is: 1. configure xtal1 and xtal2 for analog i/o. 2. disable the xtal1 and xtal2 digital output drivers by writing 1s to the appropriate bits in the port latch register. 3. configure and enable the external oscillator. 4. wait at least 1 ms. 5. poll for xtlvld > 1. 6. switch the system clock to the external oscillator. 13 pf 13 pf 32 khz xtal1 xtal2 10 m ? www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 169 c8051f39x/37x 26.5.2. external rc example if an rc network is used as an external oscillator so urce for the mcu, the circ uit should be configured as shown in figure 26.1, ?rc mode?. the capacitor should be no greater than 100 pf; however, for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to deter- mine the required external oscilla tor frequency control va lue (xfcn) in the oscxcn register, first select the rc network value to prod uce the desired frequency of oscilla tion, according to equation , where f = the frequency of oscillation in mhz, c = the capacitor value in pf, and r = the pull-up resistor value in k ? .. equation 26.1. rc mode oscillator frequency for example: if the frequency desired is 100 khz, let r = 246 k ? and c = 50 pf: f = 1.23( 10 3 )/rc=1.23(10 3 ) / [ 246 x 50 ] = 0.1 mhz = 100 khz referring to the table in sfr definition 26.5, the required xfcn setting is 010b. 26.5.3. external capacitor example if a capacitor is used as an external oscillator for t he mcu, the circuit should be configured as shown in figure 26.1, ?c mode?. the capacitor should be no greater than 100 pf; however, for very small capaci- tors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to determine the required external oscillato r frequency control value (xfcn) in th e oscxcn register, select the capaci- tor to be used and find th e frequency of oscillation according to equation , wher e f = the frequency of oscil- lation in mhz, c = the capacitor value in pf, and v dd = the mcu power supply in volts. equation 26.2. c mode oscillator frequency for example: assume v dd = 3.0 v and f = 150 khz: f = kf / (c x vdd) 0.150 mhz = kf / (c x 3.0) since the frequency of roughly 150 khz is desired, sele ct the k factor from the table in sfr definition 26.5 (oscxcn) as kf = 22: 0.150 mhz = 22 / (c x 3.0) c x 3.0 = 22 / 0.150 mhz c = 146.6 / 3.0 pf = 48.8 pf therefore, the xfcn value to use in this example is 011b and c = 50 pf. f 1.23 10 3 ? rc ? ?? ? = fkf ?? cv dd ? ?? ? = www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 170 preliminary rev. 0.71 sfr address = 0xb1; sfr page = all pages sfr definition 26.5. oscxcn: ex ternal oscillator control bit76543210 name xclkvld xoscmd[2:0] xfcn[2:0] type rr/wrr/w reset 00000000 bit name function 7 xclkvld external oscillator valid flag. provides external oscillator status and is valid at all times for all modes of opera- tion except external cmos clock mo de and external cmos clock mode with divide by 2. in these modes, xclkvld always returns 0. 0: external oscillator is unused or not yet stable. 1: external oscillator is running and stable. 6:4 xoscmd[2:0] external oscillat or mode select. 00x: external oscillator circuit off. 010: external cmos clock mode. 011: external cmos clock mode with divide-by-2 stage. 100: rc oscillator mode wit h divide-by-2 stage. 101: capacitor oscillator mo de with divide-by-2 stage. 110: crystal oscillator mode. 111: crystal oscillator mode with divide-by-2 stage. 3 unused read = 0; write = don?t care 2:0 xfcn[2:0] external oscillator frequency control bits. set according to the desired frequency for rc mode. set according to the desired k factor for c mode. xfcn crystal mode rc mode c mode 000 f ?? 20 khz f ?? 25 khz k factor = 0.87 001 20 khz ?? f ?? 58 khz 25 khz ?? f ?? 50 khz k factor = 2.6 010 58 khz ?? f ?? 155 khz 50 khz ?? f ?? 100 khz k factor = 7.7 011 155 khz ?? f ?? 415 khz 100 khz ?? f ?? 200 khz k factor = 22 100 415 khz ?? f ?? 1.1 mhz 200 khz ?? f ?? 400 khz k factor = 65 101 1.1 mhz ?? f ?? 3.1 mhz 400 khz ?? f ?? 800 khz k factor = 180 110 3.1 mhz ?? f ?? 8.2 mhz 800 khz ?? f ?? 1.6 mhz k factor = 664 111 8.2 mhz ?? f ?? 25 mhz 1.6 mhz ?? f ?? 3.2 mhz k factor = 1590 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 171 c8051f39x/37x 27. port input/output digital and analog resources are available through 17 (c8051f392/3/6/7/8/9) or 21 (c8051f390/1/4/5 and c8051f37x) i/o pins. port pins p0.0-p2.3 can be define d as general-purpose i/o (gpio), assigned to one of the internal digital resources, or assigned to an a nalog function as shown in figure 27.3. port pin p2.4 on the c8051f390/1/4/5 and c8051f37x and p2.0 on the c8051f392/3/6/7/8/9 can be used as gpio and are shared with the c2 interface data signal (c2d). the designer has complete control over which func- tions are assigned, limited only by the number of physical i/o pins . this resource assignment flexibility is achieved through the use of a priority crossbar decode r. note that the state of a port i/o pin can always be read in the corresponding port latch, regardless of the crossbar settings. the crossbar assigns the selected internal digital reso urces to the i/o pins based on the priority decoder (figure 27.3 and figure 27.4). the registers xbr0 a nd xbr1, defined in sfr definition 27.1 and sfr definition 27.2, are used to se lect internal digital functions. the port i/o cells are configured as either push-pu ll or open-drain in the port output mode registers (pnmdout, where n = 0,1). complete electrical spec ifications for port i/o are given in section ?7. electrical characteristics? on page 32. figure 27.1. port i/o functional block diagram xbr0, xbr1, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0.0 p0.7 8 port match p0mask, p0mat p1mask, p1mat uart (internal digital signals) highest priority lowest priority sysclk 2 smbus0 t0, t1 2 4 pca 2 cp0 outputs spi 4 p1 i/o cells p1.0 8 (port latches) p0 (p0.0-p0.7) (p1.0-p1.7) 8 8 p1 p2 i/o cell p2 (p2.0-p2.3*) 4 4 pnmdout, pnmdin registers p1.7 p2.0* p2.3* to analog peripherals (adc0, cp0, vref, xtal) external interrupts ex0 and ex1 *p2.0-p2.3 are only available through the crossbar on qfn24 packages. 2 smbus1 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 172 preliminary rev. 0.71 27.1. port i/o m odes of operation port pins p0.0 - p2.3 use the port i/o cell shown in figure 27.2. each port i/o cell can be configured by software for analog i/o or digital i/o using the pnmdin registers. on rese t, all port i/o ce lls default to a high impedance state with weak pull- ups enabled. until the crossbar is enabled (xbare = ?1?), both the high and low port i/o drive circuits are explicitly disabled on all crossbar pins. 27.1.1. port pins conf igured for analog i/o any pins to be used as comparator or adc input, ex ternal oscillator input/out put, vref, or idac output should be configured for analog i/o (pnmdin.n = ?1?). when a pin is configured for analog i/o, its weak pullup, digital driver, and digital receiver are disabled. port pins configured for analog i/o will always read back a value of ?0?. configuring pins as analog i/o saves power and isolates the port pin from digital interference. port pins configured as digital i/o may still be used by analog pe ripherals; however, this practice is not recom- mended and may result in measurement errors. 27.1.2. port pins configured for digital i/o any pins to be used by digital peripherals (uart, spi, smbus, etc.), external event trigger functions, or as gpio should be configured as digital i/o (pnmdin.n = ?1 ?). for digital i/o pins, one of two output modes (push-pull or open-drain) must be selected using the pnmdout registers. push-pull outputs (pnmdout.n = ?1?) drive the port pad to the vdd or gnd supply rails based on the out- put logic value of the port pin. open-drain outputs have the high side driver disabled; therefore, they only drive the port pad to gnd when the output logic valu e is ?0? and become high impedance inputs (both high low drivers turned off) when the output logic value is ?1?. when a digital i/o cell is placed in the high impedance state, a weak pull-up transistor pulls the port pad to the vdd supply voltage to ensure th e digital input is at a defined logic state. weak pull-ups are disabled when the i/o cell is driven to gnd to minimize powe r consumption, and they may be globally disabled by setting weakpud to ?1?. the user should ensure that digi tal i/o are always interna lly or extern ally pulled or driven to a valid logic state to minimize power cons umption. port pins configured for digital i/o always read back the logic state of the port pad, regard less of the output logic value of the port pin. figure 27.2. port i/o cell block diagram gnd vdd vdd (weak) port pad to/from analog peripheral pxmdin.x (1 for digital) (0 for analog) px.x ? output logic value (port latch or crossbar) xbare (crossbar enable) px.x ? input logic value (reads 0 when pin is conf igured as an analog i/o) pxmdout.x (1 for push-pull) (0 for open-drain) weakpud (weak pull-up disable) www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 173 c8051f39x/37x 27.2. assigning port i/o pins to analog and digital functions port i/o pins p0.0 - p2.3 can be assigned to various ana log, digital, and external interrupt functions. the port pins assigned to analog functions should be config ured for analog i/o, and port pins assigned to digi- tal or external interrupt functions should be configured for digital i/o. 27.2.1. assigning port i/o pins to analog functions table 27.1 shows all available analog func tions that require port i/o assignments. port pins selected for these analog functions should have their corresponding bit in pnskip set to ?1?. this reserves the pin for use by the analog function and does not allow it to be claimed by the crossbar. table 27.1 shows the potential mapping of port i/o to each analog function. table 27.1. port i/o assignment for analog functions analog function potentially assignable port pins sfr(s) used for assignment adc input p0.0 - p2.3 amx0p, amx0n, pnskip, pnmdin comparator0 input p0.0 - p2.3 cpt0mx, pnskip, pnmdin voltage reference (vref0) p0.0 ref0cn, pnskip, pnmdin current dac output (ida0) p0.1 ida0cn, pnskip, pnmdin current dac output (ida1) p1.0 (20-pin devices) p1.2 (24-pin devices) ida1cn, pnskip, pnmdin external oscillator in crystal m ode (xtal1) p0.2 oscxcn, pnskip, pnmdin external oscillator in rc, c, or cr ystal mode (xtal2) p0.3 oscxcn, pnskip, pnmdin www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 174 preliminary rev. 0.71 27.2.2. assigning port i/o pins to digital functions any port pins not assigned to analog functions may be assigned to digital functions or used as gpio. most digital functions rely on the crossbar for pin assi gnment; however, some digital functions bypass the crossbar in a manner similar to the analog functions listed above. port pins used by these digital func- tions and any port pins selected for use as gpio should have their corresponding bit in pnskip set to ?1?. table 27.2 shows all available digital functions and t he potential mapping of port i/o to each digital function. table 27.2. port i/o assignment for digital functions digital function potentially assignable port pins sfr(s) used for assignment uart0, spi0, smbus0, smbus1, cp0, cp0a, sysclk, pca0 (cex0-2 and eci), t0 or t1. any port pin available for assignment by the crossbar. this includes p0.0 - p2.3 pins which have their pnskip bit set to ?0?. note: the crossbar will always assign uart0 pins to p0.4 and p0.5. xbr0, xbr1 any pin used for gpio p0.0 - p2.4 p0skip, p1skip, p2skip www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 175 c8051f39x/37x 27.2.3. assigning port i/o pins to external event trigger functions external event trigger functions can be used to trigger an interrupt or wake the device from a low power mode when a transition occurs on a digital i/o pin. the event trigger functions do not require dedicated pins and will function on bot h gpio pins (pnskip = ?1?) and pins in use by the crossbar (pnskip = ?0?). external event trigger functions cannot be used on pi ns configured for analog i/o. table 27.3 shows all available external event trigger functions. table 27.3. port i/o assignment for external event trigger functions event trigger function potentially assignable port pins sfr(s) used for assignment external interrupt 0 p0.0 - p0.7 it01cf external interrupt 1 p0.0 - p0.7 it01cf port match p0.0 - p1.7 p0mask, p0mat p1mask, p1mat www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 176 preliminary rev. 0.71 27.3. priority crossbar decoder the priority crossbar decoder (figure 27.3) assigns a priority to each i/o function, starting at the top with uart0. when a digital resource is selected, the leas t-significant unassigned port pin is assigned to that resource (excluding uart0, which is a lways at pins 4 and 5). if a port pin is assigned, the crossbar skips that pin when assigning the next se lected resource. additionally, the crossbar will skip port pins whose associated bits in the pnskip registers are set. the pn skip registers allow software to skip port pins that are to be used for analog input, dedicated functions, or gpio. important note on crossbar configuration: if a port pin is claimed by a peripheral without use of the crossbar, its corresponding pnskip bit should be set. this applies to p0.0 if vref is used, p0.3 and/or p0.2 if the external oscillat or circuit is enabled, p0.6 if the adc or idac is configured to use the external conversion start signal (cnvstr), and any selected adc or comparator inputs. the crossbar skips selected pins as if they were already assi gned, and moves to the next unassigned pin. figure 27.3 shows all of the potential peripheral-to- pin assignments available to the crossbar. note that this does not mean any peripheral can always be assign ed to the highlighted pins. the actual pin assign- ments are determined by the priori ty of the enabled peripherals. figure 27.3. crossbar priority decoder - possible pin assignments vref ida0 x1 x2 cnvstr ida1 vref ida0 x1 x2 cnvstr ida1 eesda 5 eescl 5 0123456701234567 0 4 1 3 2 3 3 3 4 3 sysclk cex0 cex1 cex2 eci notes: 1. nss is only pinned out in 4-wire spi mode 2. smbus pins can be re-ordered using smbtc register 3. pins p2.1-p2.4 only on qfn24 package 4. pin 2.0 unavailable on crossbar in qfn20 package 5. c8051f37x only special function signals are not assigned by the crossbar. when these signals are enabled, the crossbar must be manually configured to skip their corresponding port pins. port pin potentially available to peripheral sf signals t1 p2 cp0a t0 tx0 cp0 pin not available for crossbar peripherals. scl0 2 p0 p1 sda1 2 scl1 2 sf signals (20-pin) sf signals (24-pin) pin i/o nss 1 sck miso mosi rx0 sda0 2 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 177 c8051f39x/37x registers xbr0 and xbr1 are used to assign the digital i/o resources to the physical i/o port pins. note that when the smbus is selected, the crossbar assigns both pins associated with the smbus (sda and scl); when the uart is selected, the crossbar assign s both pins associated with the uart (tx and rx). uart0 pin assignments are fixed for bootloading purp oses: uart tx0 is always assigned to p0.4; uart rx0 is always assigned to p0.5. standard port i/os appear contiguously after the prioritized functions have been assigned. figure 27.4 shows an example of the resulting pin assignments of the device with uart0, smbus, and cex0 enabled, the xtal1 (p0.2) and xtal2 (p0.3) pins skipped (p0skip = 0x0c). uart0 is the highest priority and it will be assigned first. the uart can on ly appear on p0.4 and p0.5, so that is where it is assigned. the next-highest enabled peripheral is smbus0. p0.0 and p0.1 are free, so smbus0 takes these two pins. the last peripheral enabled is the pca?s cex0 pin. p0.0, p0.1, p0.4 and p0.5 are already occupied by higher-priority peripherals. additionally, p0.2 and p0.3 are set to be skipped by the crossbar. the cex0 signal ends up getting routed to p0.6, as it is the next available pin. the other pins on the device are available for use as general-purpose digital i/o or analog functions. figure 27.4. crossbar priority decoder example important notes: the spi can be operated in either 3-wire or 4-wire modes, pending the state of the nssmd1?nssmd0 bits in register spi0cn. according to the spi mode, the nss signal may or may not be routed to a port pin. the order in which smbus pins are assigned is defined by the smbnswap bits in the smbtc register. vref ida0 x1 x2 cnvstr ida1 vref ida0 x1 x2 cnvstr ida1 eesda 5 eescl 5 01234567012345670 1 2 2 2 3 2 4 2 00110000000000000000 notes: 1. nss is only pinned out in 4-wire spi mode 2. smbus pins can be re-ordered using smbtc register 3. pins p2.1-p2.4 only on qfn24 package 4. pin 2.0 unavailable on crossbar in qfn20 package 5. c8051f37x only sda1 2 p1skip[0:7] special function signals are not assigned by the crossbar. when these signals are enabled, the crossbar must be manually configured to skip their corresponding port pins. port pin potentially available to peripheral sf signals p0skip[0:7] p2skip[0:3] p0 p1 sf signals (20-pin) sf signals (24-pin) cp0 sda scl cp0a rx0 pin not available for crossbar peripherals. scl1 2 sck miso mosi p2 pin i/o tx0 nss 1 sysclk cex0 cex1 cex2 eci t1 t0 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 178 preliminary rev. 0.71 27.4. port i/o initialization port i/o initialization cons ists of the following steps: 1. select the input mode (analog or digital) for all port pins, using the port input mode register (pnmdin). 2. select the output mode (open-drain or push-pull) fo r all port pins, using the port output mode register (pnmdout). 3. select any pins to be skipped by the i/o cr ossbar using the port skip registers (pnskip). 4. assign port pins to desired peripherals. 5. enable the cro ssbar (xbare = ?1?). all port pins must be configured as either analog or digital inputs. any pins to be used as comparator or adc inputs should be configured as an analog inputs. when a pin is configured as an analog input, its weak pullup, digital driver, and digital receiver are disabled. this process saves power and reduces noise on the analog input. pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. additionally, all analog input pins should be config ured to be skipped by the crossbar (accomplished by setting the associated bits in pnskip). port input mode is set in the pnmdin register, where a ?1? indicates a digital input, and a ?0? indicates an analog input. all pi ns default to digital inputs on reset. see sfr defini- tion 27.8 for the pnmdin register details. the output driver characteristics of the i/o pins ar e defined using the port output mode registers (pnmd- out). each port output driver can be configured as either open drain or pus h-pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. when the weakpud bi t in xbr1 is ?0?, a weak pullup is enabled for all port i/o con- figured as open-drain. w eakpud does not affect the push-pull port i/o. furthe rmore, the weak pullup is turned off on an output that is driving a ?0? to avoid unnecessary power dissipation. registers xbr0 and xbr1 must be loaded with the approp riate values to select the digital i/o functions required by the design. setting the xbare bit in xbr1 to ?1? enables the cross bar. until the crossbar is enabled, the external pins remain as standard port i/o (in input mode), regardless of the xbrn register settings. for given xbrn register settings, one can de termine the i/o pin-out us ing the priority decode table; as an alternative, the confi guration wizard utility of the silicon labs ide software will determine the port i/o pin-assignments based on the xbrn register settings. the crossbar must be enabled to us e port pins as standard port i/o in output mode. port output drivers are disabled while the crossbar is disabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 179 c8051f39x/37x sfr address = 0xe1; sfr page = all pages sfr definition 27.1. xbr0: port i/o crossbar register 0 bit76543210 name eepue smb1e cp0ae cp0e syscke smb0e spi0e urt0e type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 eepue eeprom pullup enable. 0: on-chip strong pullups not active. 1: on-chip strong pullups active on pins p2.2 and p2.3. 6smb1e smbus1 i/o enable. 0: smbus1 i/o unavailable at port pins. 1: smbus1 i/o rout ed to port pins. 5 cp0ae comparator0 asynchronous output enable. 0: asynchronous cp0 unavailable at port pin. 1: asynchronous cp0 routed to port pin. 4cp0e comparator0 output enable. 0: cp0 unavailable at port pin. 1: cp0 routed to port pin. 3 syscke /sysclk output enable. 0: /sysclk unavailable at port pin. 1: /sysclk output routed to port pin. 2smb0e smbus0 i/o enable. 0: smbus0 i/o unavailable at port pins. 1: smbus0 i/o rout ed to port pins. 1 spi0e spi i/o enable. 0: spi i/o unavailable at port pins. 1: spi i/o routed to port pins. note that the spi can be assigned either 3 or 4 gpio pins. 0urt0e uart i/o output enable. 0: uart i/o unavailable at port pin. 1: uart tx0, rx0 routed to port pins p0.4 and p0.5. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 180 preliminary rev. 0.71 sfr address = 0xe2; sfr page = all pages sfr definition 27.2. xbr1: port i/o crossbar register 1 bit7 6543210 name weakpud xbare t1e t0e ecie pca0me[1:0] type r/w r/w r/w r/w r/w r r/w r/w reset 0 0000000 bit name function 7 weakpud port i/o weak pullup disable. 0: weak pullups enabled (except for ports whose i/o are con- figured for analog mode). 1: weak pullups disabled. 6 xbare crossbar enable. 0: crossbar disabled. 1: crossbar enabled. 5t1e t1 enable. 0: t1 unavailable at port pin. 1: t1 routed to port pin. 4t0e t0 enable. 0: t0 unavailable at port pin. 1: t0 routed to port pin. 3ecie pca0 external counter input enable. 0: eci unavailable at port pin. 1: eci routed to port pin. 2 unused read = 0b; write = don?t care. 1:0 pca0me[1:0] pca module i/o enable bits. 00: all pca i/o unavailable at port pins. 01: cex0 routed to port pin. 10: cex0, cex1 routed to port pins. 11: cex0, cex1, cex2 routed to port pins. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 181 c8051f39x/37x 27.5. port match port match functionality allows system events to be tr iggered by a logic value change on p0 or p1. a soft- ware controlled value stored in the pnmatch registers specifies the expected or normal logic values of p0 and p1. a port mismatch event occurs if the logic levels of the port?s input pins no longer match the soft- ware controlled value. this allows software to be notified if a certain change or pattern occurs on p0 or p1 input pins regardless of the xbrn settings. the pnmask registers can be used to individually select which p0 and p1 pins should be compared against the pnmatch regist ers. a port mismatch event is gene rated if (p0 & p0m ask) does not equal (p0match & p0mask) or if (p1 & p1mask) does not equal (p1match & p1mask). a port mismatch event may be used to generate an interrupt or wake the device from a low power mode, such as idle or suspend. see the interrupts and power options chapte rs for more details on interrupt and wake-up sources. sfr address = 0xfe; sfr page = all pages sfr definition 27.3. p0mask: port 0 mask register bit76543210 name p0mask[7:0] type r/w reset 00000000 bit name function 7:0 p0mask[7:0] port 0 mask value. selects p0 pins to be compared to the corresponding bits in p0mat. 0: p0.n pin logic value is ignored and cannot cause a port mismatch event. 1: p0.n pin logic value is compared to p0mat.n. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 182 preliminary rev. 0.71 sfr address = 0xfd; sfr page = all pages sfr address = 0xee; sfr page = all pages sfr definition 27.4. p0mat: port 0 match register bit76543210 name p0mat[7:0] type r/w reset 11111111 bit name function 7:0 p0mat[7:0] port 0 match value. match comparison value used on port 0 for bits in p0mask which are set to ?1?. 0: p0.n pin logic value is compared with logic low. 1: p0.n pin logic value is compared with logic high. sfr definition 27.5. p1mask: port 1 mask register bit76543210 name p1mask[7:0] type r/w reset 00000000 bit name function 7:0 p1mask[7:0] port 1 mask value. selects p1 pins to be compared to the corresponding bits in p1mat. 0: p1.n pin logic value is ignored and cannot cause a port mismatch event. 1: p1.n pin logic value is compared to p1mat.n. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 183 c8051f39x/37x sfr address = 0xed; sfr page = all pages 27.6. special function re gisters for accessing an d configuring port i/o all port i/o are accessed through corresponding spec ial function registers (sfrs) that are both byte addressable and bit addressable. when writing to a port, the value writt en to the sfr is latched to main- tain the output data value at each pin. when reading, the logic levels of the port's input pins are returned regardless of the xbrn settings (i.e., even when the pi n is assigned to another signal by the crossbar, the port register can always read its corresponding port i/ o pin). the exception to this is the execution of the read-modify-write instructio ns that target a port latch register as the destination. the read-modify-write instructions when operating on a port sfr are the fo llowing: anl, orl, xrl, jbc, cpl, inc, dec, djnz and mov, clr or setb, when the destination is an indi vidual bit in a port sfr. for these instructions, the value of the latch register (not the pin) is read, modified, and written back to the sfr. each port has a corresponding pnskip register which allo ws its individual port pins to be assigned to dig- ital functions or skipped by the crossbar. all port pins used for analog functions, gpio, or dedicated digital functions such as the emif should have their pnskip bit set to ?1?. the port input mode of the i/o pins is defined using the port input mode registers (pnmdin). each port cell can be configured for analog or digital i/o. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is p2.4, which can only be used for digital i/o. the output driver characteristics of the i/o pins ar e defined using the port output mode registers (pnmd- out). each port output driver can be configured as either open drain or pus h-pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. sfr definition 27.6. p1mat: port 1 match register bit76543210 name p1mat[7:0] type r/w reset 11111111 bit name function 7:0 p1mat[7:0] port 1 match value. match comparison value used on port 1 for bits in p1mask which are set to ?1?. 0: p1.n pin logic value is compared with logic low. 1: p1.n pin logic value is compared with logic high. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 184 preliminary rev. 0.71 sfr address = 0x80; sfr page = all pages; bit addressable sfr address = 0xf1; sfr page = all pages sfr definition 27.7. p0: port 0 bit76543210 name p0[7:0] type r/w reset 11111111 bit name description write read 7:0 p0[7:0] port 0 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p0.n port pin is logic low. 1: p0.n port pin is logic high. sfr definition 27.8. p0mdi n: port 0 input mode bit76543210 name p0mdin[7:0] type r/w reset 11111111 bit name function 7:0 p0mdin[7:0] analog configuration bits for p0.7?p0.0 (respectively). port pins configured for anal og mode have their weak pul- lup, digital driver, and digital receiver disabled. 0: corresponding p0.n pin is configured for analog mode. 1: corresponding p0.n pin is not configured for analog mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 185 c8051f39x/37x sfr address = 0xa4; sfr page = all pages sfr address = 0xd4; sfr page = all pages sfr definition 27.9. p0mdo ut: port 0 output mode bit76543210 name p0mdout[7:0] type r/w reset 00000000 bit name function 7:0 p0mdout[7:0] output configuration bits for p0.7?p0.0 (respectively). these bits are ignored if the corresponding bit in register p0mdin is logic 0. 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull. sfr definition 27.10. p0skip: port 0 skip bit76543210 name p0skip[7:0] type r/w reset 00000000 bit name function 7:0 p0skip[7:0] port 0 crossbar skip enable bits. these bits select port 0 pins to be skipped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p0.n pin is not skipped by the crossbar. 1: corresponding p0.n pin is skipped by the crossbar. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 186 preliminary rev. 0.71 sfr address = 0x90; sfr page = all pages; bit addressable sfr address = 0xf2; sfr page = all pages sfr definition 27.11. p1: port 1 bit76543210 name p1[7:0] type r/w reset 11111111 bit name description write read 7:0 p1[7:0] port 1 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p1.n port pin is logic low. 1: p1.n port pin is logic high. sfr definition 27.12. p1mdin: port 1 input mode bit76543210 name p1mdin[7:0] type r/w reset 11111111 bit name function 7:0 p1mdin[7:0] analog configuration bits for p1.7?p1.0 (respectively). port pins configured for anal og mode have their weak pul- lup, digital driver, and digital receiver disabled. 0: corresponding p1.n pin is configured for analog mode. 1: corresponding p1.n pin is not configured for analog mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 187 c8051f39x/37x sfr address = 0xa5; sfr page = all pages sfr address = 0xd5; sfr page = all pages sfr definition 27.13. p1mdout: port 1 output mode bit76543210 name p1mdout[7:0] type r/w reset 00000000 bit name function 7:0 p1mdout[7:0] output configuration bits for p1.7?p1.0 (respectively). these bits are ignored if the corresponding bit in register p1mdin is logic 0. 0: corresponding p1.n output is open-drain. 1: corresponding p1.n output is push-pull. sfr definition 27.14. p1skip: port 1 skip bit76543210 name p1skip[7:0] type r/w reset 00000000 bit name function 7:0 p1skip[7:0] port 1 crossbar skip enable bits. these bits select port 1 pins to be skipped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p1.n pin is not skipped by the crossbar. 1: corresponding p1.n pin is skipped by the crossbar. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 188 preliminary rev. 0.71 sfr address = 0xa0; sfr page = a ll pages; bit addressable sfr address = 0xf3; sfr page = all pages sfr definition 27.15. p2: port 2 bit76543210 name p2[4:0] type rrr r/w reset 00011111 bit name description write read 7:5 unused unused. don?t care 000b 4:0 p2[4:0] port 2 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p2.n port pin is logic low. 1: p2.n port pin is logic high. note: pins p2.1-p2.4 are only available in qfn24-packaged devices. sfr definition 27.16. p2mdin: port 2 input mode bit76543210 name p2mdin[7:0] type rrrr r/w reset 00001111 bit name function 7:4 unused read = 0000b; write = don?t care 3:0 p2mdin[3:0] analog configuration bits fo r p2.3?p2.0 (respectively). port pins configured for analog mode have their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p2.n pin is configured for analog mode. 1: corresponding p2.n pin is no t configured for analog mode. note: pins p2.1-p2.4 are only available in qfn24-packaged devices. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 189 c8051f39x/37x sfr address = 0xa6; sfr page = all pages sfr address = 0xd6; sfr page = all pages sfr definition 27.17. p2mdout: port 2 output mode bit76543210 name p2mdout[4:0] type rrr r/w reset 00000000 bit name function 7:5 unused read = 000b; write = don?t care 4:0 p2mdout[4:0] output configuration bits for p2.4?p2.0 (respectively). these bits are ignored if the corresponding bit in register p2mdin is logic 0. 0: corresponding p2.n output is open-drain. 1: corresponding p2.n output is push-pull. note: p2.0 is not available for analog input in the qfn20-packaged devices, and p2.1-p2.4 are only available in the qfn24-packaged devices. sfr definition 27.18. p2skip: port 2 skip bit76543210 name p2skip[7:0] type rrrr r/w reset 00000000 bit name function 7:4 unused read = 0000b; write = don?t care 3:0 p2skip[3:0] port 2 crossbar skip enable bits. these bits select port 2 pins to be skipped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p2.n pin is not skipped by the crossbar. 1: corresponding p2.n pin is skipped by the crossbar. note: p2.0 is not available for crossbar peripherals in the qfn20-packaged devices, and p2.1-p2.4 are only available in the qfn24-packaged devices. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 190 preliminary rev. 0.71 28. smbus0 and smbus1 (i 2 c compatible) the smbus i/o interface is a two-wire, bi-directional serial bus. the smbus is compliant with the system management bus specification, version 1.1, and compatible with the i 2 c serial bus. the c8051f39x/37x devices contain two smbus interfaces, smbus0 and smbus1. reads and writes to the smbus by the system controlle r are byte oriented with the smbus interface auton- omously controlling the serial transfer of the data. data can be transfer red at up to 1/20th of the system clock as a master or slave (this can be faster than allowed by the smbus specification, depending on the system clock used). a method of extending the clo ck-low duration is available to accommodate devices with different speed capa bilities on the same bus. the smbus may operate as a master and/or slave, and may function on a bus with multiple masters. the smbus provides control of sda (serial data), scl (ser ial clock) generation and sy nchronization, arbitration logic, and start/stop control and generation. the smbus peripherals can be fully driven by software (i.e., software accepts/rejects slave addresses, and generates acks), or hardware slave address recogni- tion and automatic ack generation can be enabled to minimize software overhead. a block diagram of the smbus0 peripheral and the associated sfrs is shown in figure 28.1. smbus1 is identical, with the excep- tion of the available timer options for the clock sour ce, and the timer used to implement the scl low time- out feature. refer to the specific sfr definitions for more details. figure 28.1. smbus0 block diagram data path control smbus control logic c r o s s b a r scl filter n sda control scl control interrupt request port i/o smb0cn s t a a c k r q a r b l o s t a c k s i t x m o d e m a s t e r s t o 01 00 10 11 t0 overflow t1 overflow tmr2h overflow tmr2l overflow smb0cf e n s m b i n h b u s y e x t h o l d s m b t o e s m b f t e s m b c s 1 s m b c s 0 0 1 2 3 4 5 6 7 smb0dat sda filter n smb0adr s l v 4 s l v 2 s l v 1 s l v 0 g c s l v 5 s l v 6 s l v 3 smb0adm s l v m 4 s l v m 2 s l v m 1 s l v m 0 e h a c k s l v m 5 s l v m 6 s l v m 3 arbitration scl synchronization hardware ack generation scl generation (master mode) sda control hardware slave address recognition irq generation www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 191 c8051f39x/37x 28.1. supporting documents it is assumed the reader is fam iliar with or has access to th e following supporting documents: 1. the i 2 c-bus and how to use it (including s pecifications), philips semiconductor. 2. the i 2 c-bus specification?version 2.0, philips semiconductor. 3. system management bus specification? version 1.1, sbs implementers forum. 28.2. smbus configuration figure 28.2 shows a typical smbus configuration. th e smbus specification allows any recessive voltage between 3.0 v and 5.0 v; different devices on the bus may operate at different voltage levels. however, the maximum voltage on any port pin must conform to tabl e 7.1. the bi-directional scl (serial clock) and sda (serial data) lines must be connected to a positive power supply voltage through a pullup resistor or similar circuit. every device connected to the bus must hav e an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high (rec essive state) when the bus is free. the maximum number of devices on the bus is limit ed only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. figure 28.2. typical smbus configuration 28.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addres sed slave transmitter to a master receiver (read). the master device initiates both types of data transfer s and provides the serial clock pulses on scl. the smbus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. if two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbi tration. it is not necessary to specify one device as the master in a system; any device who transmits a start and a slave address becomes the master for the duration of that transfer. a typical smbus transaction consists of a start cond ition followed by an address byte (bits7?1: 7-bit slave address; bit0: r/w direction bit), one or more bytes of data, and a stop condition. bytes that are received (by a master or slave) are acknowledg ed (ack) with a low sda during a high scl (see figure 28.3). if the receiving device does not ack, the tran smitting device will read a nack (not acknowl- edge), which is a high sda during a high scl. the direction bit (r/w) occupies the least-significant bit position of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. 3.0v < vdd < 3.6v master device slave device 1 slave device 2 sda scl www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 192 preliminary rev. 0.71 all transactions are initiated by a master, with one or more addressed slave devices as the target. the master generates the start condition and then transmit s the slave address and dire ction bit. if the trans- action is a write operation from th e master to the slave, the master transmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operations , the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to term inate the transaction and free the bu s. figure 28.3 illustrates a typical smbus transaction. figure 28.3. smbus transaction 28.3.1. transmitter vs. receiver on the smbus communications interface, a device is the ?transmitter? when it is sending an address or data byte to another device on the bus. a device is a ?receiver? when an address or data byte is being sent to it from another device on the bus. the transmitter controls the sda line during the address or data byte. after each byte of address or data information is se nt by the transmitter, the receiver sends an ack or nack bit during the ack phase of the transfer, dur ing which time the receiver controls the sda line. 28.3.2. arbitration a master may start a transfer only if the bus is free. th e bus is free after a stop condition or after the scl and sda lines remain high for a specified time (see section ?28.3.5. scl high (smbus free) timeout? on page 193). in the event that two or more devices attempt to begin a transfer at the same time, an arbitra- tion scheme is employed to force one master to give up the bus. the master devices continue transmitting until one attempts a high while the other transmit s a low. since the bus is open-drain, the bus will be pulled low. the master attempting th e high will detect a low sda and lo se the arbitration. the winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. this arbitration scheme is non-destru ctive: one device always wins, and no data is lost. 28.3.3. clock low extension smbus provides a clock synchronizati on mechanism, similar to i2c, wh ich allows devices with different speed capabilities to coexist on the bus. a clock-low extension is used du ring a transfer in order to allow slower slave devices to communica te with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. 28.3.4. scl low timeout if the scl line is held low by a slave device on the bus, no further communication is possible. furthermore, the master cannot force the scl line high to correct th e error condition. to solve this problem, the smbus protocol specifies that devices participating in a tran sfer must detect any clock cycle held low longer than 25 ms as a ?timeout? condition. devices that have det ected the timeout condition must reset the communi- cation no later than 10 ms after detecting the timeout condition. for the smbus0 interface, timer 3 is used to implement scl low timeouts. timer 4 is used on the smbus1 interface for scl low timeouts. the scl low timeout feature is enabled by setting the smbntoe bit in smbncf. the associated timer is forced to reload when scl is high, and allo wed to count when scl is sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 193 c8051f39x/37x low. with the associated timer enabled and configur ed to overflow after 25 ms (and smbntoe set), the timer interrupt service routine can be used to reset (disable and re-enable) the smbus in the event of an scl low timeout. 28.3.5. scl high (smbus free) timeout the smbus specification stipulates th at if the scl and sda lines remain high for more that 50 s, the bus is designated as free. when the smbnfte bit in smbn cf is set, the bus will be co nsidered free if scl and sda remain high for more than 10 smbus clock source periods (as defined by the timer configured for the smbus clock source). if the smbus is waiting to generate a master start, the start will be generated following this timeout. a clock source is required for free timeout detection, even in a slave-only implemen- tation. 28.4. using the smbus the smbus can operate in both master and slave modes. the interface provides timing and shifting con- trol for serial transfers; higher level protocol is de termined by user software. the smbus interface provides the following application-independent features: ? byte-wise serial data transfers ? clock signal generation on scl (master mode only) and sda data synchronization ? timeout/bus error recognition, as defined by the smb0cf configuration register ? start/stop timing, detection, and generation ? bus arbitration ? interrupt generation ? status information ? optional hardware recognition of slave address and automatic acknowledgement of address/data smbus interrupts are generated for each data byte or slave address that is transferred. when hardware acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hard- ware is acting as a data transmitter or receiver. wh en a transmitter (i.e., sending address/data, receiving an ack), this interrupt is generated after the ack cycl e so that software may read the received ack value; when receiving data (i.e., receiving address/data, send ing an ack), this interrupt is generated before the ack cycle so that software may def ine the outgoing ack value. if har dware acknowledgement is enabled, these interrupts are always generated after the ack cycle. see section 28.5 for more details on transmis- sion sequences. interrupts are also generated to indicate the beginning of a transfer when a master (start generated), or the end of a transfer when a slave (stop detected) . software should read the smbncn (smbus control register) to find the cause of the smbus interrupt. th e smbncn register is described in section 28.4.4; table 28.5 provides a quick smbncn decoding reference. 28.4.1. smbus conf iguration register the smbus configuration register (s mbncf) is used to enable the smbus master and/or slave modes, select the smbus clock source, and select the smbu s timing and timeout optio ns. when the ensmb bit is set, the smbus is enabled for all master and slave events. slave events may be disabled by setting the inh bit. with slave events inhibited, the smbus in terface will still monitor the scl and sda pins; however, the interface will nack all received addresses and will not generate any slave inte rrupts. when the inh bit is set, all slave events will be inhibited following the ne xt start (interrupts will cont inue for the duration of the current transfer). www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 194 preliminary rev. 0.71 the smbncs1?0 bits select the smbus clock source, wh ich is used only when operating as a master or when the free timeout detection is enabled. when operating as a master, overflows from the selected source determine the absolute minimum scl low and high times as defined in equation 28.1.the selected clock source may be shared by other peripherals so long as the timer is left running at all times. for exam- ple, timer 1 overflows may generate the smbus0 and smbus1 clock rates simultaneously. timer configu- ration is covered in section ?31. timers? on page 240. equation 28.1. minimum scl high and low times the selected clock source should be configured to establish the minimum scl high and low times as per equation 28.1. when the interface is operating as a master (and scl is not driven or extended by any other devices on the bus), the typical smbus bit rate is approximated by equation 28.2. equation 28.2. typical smbus bit rate figure 28.4 shows the typical scl generation described by equation 28.2. notice that t high is typically twice as large as t low . the actual scl output may vary due to other devices on the bus (scl may be extended low by slower slave devices, or driven low by contending master devices). the bit rate when operating as a master will ne ver exceed the limits defined by equation equation 28.1. figure 28.4. typical smbus scl generation setting the exthold bit extends the minimum setup and hold times for the sda line. the minimum sda setup time defines the absolute mini mum time that sda is stable before scl transitions from low-to-high. the minimum sda hold time defines the absolute minimum time that the current sda value remains stable after scl transitions from high-to-low. exthold should be set so that the minimum setup and hold times meet the smbus specification requirements of 250 ns and 300 ns, respectively. table 28.2 shows the min- table 28.1. smbus clock source selection smbncs1 smbncs0 smbus0 clock source smbus1 clock source 0 0 timer 0 overflow timer 0 overflow 0 1 timer 1 overflow timer 5 overflow 1 0 timer 2 high byte overflow timer 2 high byte overflow 1 1 timer 2 low byte overflow timer 2 low byte overflow t highmin t lowmin 1 f clocksourceoverflow ---------------- ------------------ ----------- - == bitrate f clocksourceoverflow 3 --------------- ----------------- ------------- - = scl timer source overflows scl high timeout t low t high www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 195 c8051f39x/37x imum setup and hold times for the two exthold settings. setup and hold time extensions are typically necessary when sysclk is above 10 mhz. with the smbntoe bit set, timer 3 (smbus0) and ti mer 5 (smbus1) should be configured to overflow after 25 ms in order to detect scl low timeouts (s ee section ?28.3.4. scl low timeout? on page 192). the smbus interface will force the a ssociated timer to reload while sc l is high, and allow the timer to count when scl is low. the timer interrupt service ro utine should be used to reset smbus communication by disabling and re-enabling the smbus. smbus free timeout detection can be enabled by sett ing the smbnfte bit. when this bit is set, the bus will be considered free if sda and scl remain hi gh for more than 10 smbus clock source periods (see figure 28.4). 28.4.2. smbus pin swap the smbus peripherals are assigned to pins using the priority crossbar decoder. by default, the smbus signals are assigned to port pins starting with sda on the lower-numbered pin, and scl on the next avail- able pin. the smbnswap bits in the smbtc register can be set to 1 to reverse the order in which the smbus signals are assigned. 28.4.3. smbus timing control the smbnsdd field in the smbtc register are used to restrict the detection of a start condition under certain circumstances. in some sy stems where there is significant mis-match between the impedance or the capacitance on the sda and scl lines, it may be possible for scl to fall after sda during an address or data transfer. such an event can cause a false start detection on the bus. these kind of events are not expected in a standard smbus or i2c-compliant system. in most systems th is parameter should not be adjusted, and it is recommended that it be left at its default value. by default, if the scl falling edge is detected after th e falling edge of sda (i.e. one sysclk cycle or more), the device will detect this as a start condition. the smbnsdd field is used to increase the amount of hold time that is required between sda and scl falling before a star t is recognized. an addi- tional 2, 4, or 8 sysclks can be added to prevent false start detecti on in systems where the bus condi- tions warrant this. table 28.2. minimum sda setup and hold times exthold minimum sda setup time minimum sda hold time 0 t low ? 4 system clocks or 1 system clock + s/w delay * 3 system clocks 1 11 system clocks 12 system clocks note: setup time for ack bit transmissions and the msb of all data transfers. when using software acknowledgement, the s/w delay occurs between the time smb0dat or ack is written and when si is cleared. note that if si is cleared in the same write that defines the outgoing ack value, s/w delay is zero. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 196 preliminary rev. 0.71 sfr address = 0xc1; sfr page = 0 sfr definition 28.1. smb0cf: smbus clock/configuration bit765 4 3210 name ensmb0 inh0 busy0 exthold0 smb 0toe smb0fte smb0cs[1:0] type r/w r/w r r/w r/w r/w r/w reset 000 0 0000 bit name function 7ensmb0 smbus0 enable. this bit enables the smbus0 interface when set to 1. when enabled, the interface constantly monitors the sda0 and scl0 pins. 6 inh0 smbus0 slave inhibit. when this bit is set to logic 1, the smbus0 does not generate an interrupt when slave events occur. this effectively removes the smbus0 slave from the bus. master mode interrupts are not affected. 5busy0 smbus0 busy indicator. this bit is set to logic 1 by hardware when a transfer is in progress. it is cleared to logic 0 when a st op or free-timeout is sensed. 4 exthold0 smbus0 setup and hold ti me extension enable. this bit controls the sda0 setup and hold times according to table 28.2. 0: sda0 extended setup and hold times disabled. 1: sda0 extended setup and hold times enabled. 3smb0toe smbus0 scl timeout detection enable. this bit enables scl low timeout detection. if set to logic 1, the smbus0 forces timer 3 to reload while scl0 is high and allows timer 3 to count when scl0 goes low. if timer 3 is configured to split mode, only the high byte of the timer is held in reload while scl0 is high. timer 3 should be programmed to generate interrupts at 25 ms, and the timer 3 interrupt service routine should reset smbus0 communication. 2smb0fte smbus0 free timeout detection enable. when this bit is set to logic 1, the bus will be considered free if scl0 and sda0 remain high for more than 10 smbus clock source peri- ods. 1:0 smb0cs[1:0] smbus0 clock source selection. these two bits select the smbus0 clock source, which is used to generate the smbus0 bit rate. the selected device should be config- ured according to equation 28.1. 00: timer 0 overflow 01: timer 1 overflow 10: timer 2 high byte overflow 11: timer 2 low byte overflow www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 197 c8051f39x/37x sfr address = 0xc1; sfr page = f sfr definition 28.2. smb1cf: smbus clock/configuration bit765 4 3210 name ensmb1 inh1 busy1 exthold1 smb 1toe smb1fte smb1cs[1:0] type r/w r/w r r/w r/w r/w r/w reset 000 0 0000 bit name function 7ensmb1 smbus1 enable. this bit enables the smbus1 interface when set to 1. when enabled, the interface constantly monitors the sda1 and scl1 pins. 6 inh1 smbus1 slave inhibit. when this bit is set to logic 1, the smbus1 does not generate an interrupt when slave events occur. this effectively removes the smbus1 slave from the bus. master mode interrupts are not affected. 5busy1 smbus1 busy indicator. this bit is set to logic 1 by hardware when a transfer is in progress. it is cleared to logic 0 when a st op or free-timeout is sensed. 4 exthold1 smbus1 setup and hold ti me extension enable. this bit controls the sda1 setup and hold times according to table 28.2. 0: sda1 extended setup and hold times disabled. 1: sda1 extended setup and hold times enabled. 3smb1toe smbus1 scl timeout detection enable. this bit enables scl low timeout detection. if set to logic 1, the smbus1 forces timer 4 to reload while scl1 is high and allows timer 4 to count when scl1 goes low. if timer 4 is configured to split mode, only the high byte of the timer is held in reload while scl1 is high. timer 4 should be programmed to generate interrupts at 25 ms, and the timer 4 interrupt service routine should reset smbus1 communication. 2smb1fte smbus1 free timeout detection enable. when this bit is set to logic 1, the bus will be considered free if scl1 and sda1 remain high for more than 10 smbus clock source peri- ods. 1:0 smb1cs[1:0] smbus1 clock source selection. these two bits select the smbus1 clock source, which is used to generate the smbus1 bit rate. the selected device should be config- ured according to equation 28.1. 00: timer 0 overflow 01: timer 5 overflow 10: timer 2 high byte overflow 11: timer 2 low byte overflow www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 198 preliminary rev. 0.71 sfr address = 0xc7; sfr page = all pages sfr definition 28.3. smbtc: sm bus timing and pin control bit7 6 543210 name smb1swap smb0swap smb1sdd[1:0] smb0sdd[1:0] type r/w r/w r/w r/w r/w r/w reset 0 0 000000 bit name function 7smb1swap smbus1 swap pins this bit swaps the order of the smbus1 pins on the cross- bar. this should be set to 1 when accessing the eeprom. 0: sda1 is mapped to the lower-numbered port pin, and scl1 is mapped to the higher-numbered port pin. 1: scl1 is mapped to the lower-numbered port pin, and sda1 is mapped to the higher-numbered port pin. 6smb0swap smbus0 swap pins this bit swaps the order of the smbus1 pins on the cross- bar. this should be set to 1 when accessing the eeprom. 0: sda0 is mapped to the lower-numbered port pin, and scl0 is mapped to the higher-numbered port pin. 1: scl0 is mapped to the lower-numbered port pin, and sda0 is mapped to the higher-numbered port pin. 5:4 reserved must write 00b. 3:2 smb1sdd[1:0] smbus1 start detection window these bits increase the hold time requirement between sda falling and scl falling for start detection. 00: no additional hold ti me requirement (0-1 sysclk). 01: increase hold time window to 2-3 sysclks. 10: increase hold time window to 4-5 sysclks. 11: increase hold time window to 8-9 sysclks. 1:0 smb0sdd[1:0] smbus0 start detection window these bits increase the hold time requirement between sda falling and scl falling for start detection. 00: no additional hold time window (0-1 sysclk). 01: increase hold time window to 2-3 sysclks. 10: increase hold time window to 4-5 sysclks. 11: increase hold time window to 8-9 sysclks. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 199 c8051f39x/37x 28.4.4. smbncn control register smbncn is used to control the interface and to provid e status information (see sfr definition 28.4). the higher four bits of smbncn (master, txmode, sta, and sto) form a status vector that can be used to jump to service routines. master indicates whether a device is the master or slave during the current transfer. txmode indicates whether the device is tr ansmitting or receiving data for the current byte. sta and sto indicate that a start and/or stop ha s been detected or generated since the last smbus interrupt. sta and sto are also used to generate start and stop conditions when operating as a mas- ter. writing a 1 to sta will cause the smbus interface to enter master mode and generate a start when the bus becomes free (sta is not cleared by hardwar e after the start is generated). writing a 1 to sto while in master mode will cause the interface to generate a stop and end the current transfer after the next ack cycle. if sto and sta ar e both set (while in master mode ), a stop followed by a start will be generated. the arblost bit indicates that the interface has lost an arbitration. this may occur anytime the interface is transmitting (master or slave). a lost arbitration while operating as a slave indicates a bus error condi- tion. arblost is cleared by hardware each time si is cleared. the si bit (smbus interrupt flag) is set at the beginnin g and end of each transfer, after each byte frame, or when an arbitration is lost; see table 28.3 for more details. important note about the si bit: the smbus interface is stalled while si is set; thus scl is held low, and the bus is stalled until software clears si. 28.4.4.1. software ack generation when the ehack bit in register smbn adm is cleared to 0, the firmware on the device must detect incom- ing slave addresses and ack or nack the slave addres s and incoming data bytes. as a receiver, writing the ack bit defines the outgoing ack value; as a tr ansmitter, reading the ack bit indicates the value received during the last ack cycle. ackrq is set each ti me a byte is received, in dicating that an outgoing ack value is needed. when ackrq is set, software should write the desired outgoing value to the ack bit before clearing si. a nack will be g enerated if software does not writ e the ack bit before clearing si. sda will reflect the defined ack value immediately following a write to the ack bit; however scl will remain low until si is cleared. if a received slave address is not ackn owledged, further slave events will be ignored until the next start is detected. 28.4.4.2. hardwa re ack generation when the ehack bit in register smb0adm is set to 1, automatic slave address recognition and ack gen- eration is enabled. more detail about automatic slave address recognition can be found in section 28.4.5. as a receiver, the value currently specified by the ac k bit will be automatically sent on the bus during the ack cycle of an incoming data byte. as a transmitter, reading the ack bit indicates the value received on the last ack cycle. the ackrq bit is not used when hardware ack generation is enabled. if a received slave address is nacked by hardware, further sl ave events will be ignored until the next start is detected, and no interrupt will be generated. table 28.3 lists all sources for hardware changes to the smbncn bits. refer to table 28.5 for smbus sta- tus decoding using the smbncn register. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 200 preliminary rev. 0.71 sfr address = 0xc0; sfr pa ge = 0; bit-addressable sfr definition 28.4. smb0cn: smbus control bit 7 6 5 4 3 2 1 0 name master0 txmode0 sta0 sto0 ackrq0 arblost0 ack0 si0 type r r r/w r/w r r r/w r/w reset 00000 000 bit name description read write 7master0 smbus0 master/slave indicator. this read-only bit indicates when the smbus0 is operating as a master. 0: smbus0 operating in slave mode. 1: smbus0 operating in master mode. n/a 6 txmode0 smbus0 transmit mode indicator. this read-only bit indicates when the smbus0 is operating as a transmitter. 0: smbus0 in receiver mode. 1: smbus0 in transmitter mode. n/a 5sta0 smbus0 start flag. 0: no start or repeated start detected. 1: start or repeated start detected. 0: no start generated. 1: when configured as a master, initiates a start or repeated start. 4sto0 smbus0 stop flag. 0: no stop condition detected. 1: stop condition detected (if in slave mode) or pending (if in master mode). 0: no stop condition is transmitted. 1: when configured as a master, causes a stop condition to be transmit- ted after the next ack cycle. cleared by hardware. 3 ackrq0 smbus0 acknowledge request. 0: no ack requested 1: ack requested n/a 2arblost0 smbus0 arbitration lost indicator. 0: no arbitration error. 1: arbitration lost n/a 1ack0 smbus0 acknowledge. 0: nack received. 1: ack received. 0: send nack 1: send ack 0si0 smbus0 interrupt flag. this bit is set by hardware under the conditions listed in table 28.3. si0 must be cleared by software. while si0 is set, scl0 is held low and the smbus0 is stalled. 0: no interrupt pending 1: interrupt pending 0: clear interrupt, and ini- tiate next state machine event. 1: force interrupt. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 201 c8051f39x/37x sfr address = 0xc0; sfr page = f; bit-addressable sfr definition 28.5. smb1cn: smbus control bit 7 6 5 4 3 2 1 0 name master1 txmode1 sta1 sto1 ackrq1 arblost1 ack1 si1 type r r r/w r/w r r r/w r/w reset 00000 000 bit name description read write 7master1 smbus1 master/slave indicator. this read-only bit indicates when the smbus1 is operating as a master. 0: smbus1 operating in slave mode. 1: smbus1 operating in master mode. n/a 6 txmode1 smbus1 transmit mode indicator. this read-only bit indicates when the smbus1 is operating as a transmitter. 0: smbus1 in receiver mode. 1: smbus1 in transmitter mode. n/a 5sta1 smbus1 start flag. 0: no start or repeated start detected. 1: start or repeated start detected. 0: no start generated. 1: when configured as a master, initiates a start or repeated start. 4sto1 smbus1 stop flag. 0: no stop condition detected. 1: stop condition detected (if in slave mode) or pending (if in master mode). 0: no stop condition is transmitted. 1: when configured as a master, causes a stop condition to be transmit- ted after the next ack cycle. cleared by hardware. 3 ackrq1 smbus1 acknowledge request. 0: no ack requested 1: ack requested n/a 2arblost1 smbus1 arbitration lost indicator. 0: no arbitration error. 1: arbitration lost n/a 1ack1 smbus1 acknowledge. 0: nack received. 1: ack received. 0: send nack 1: send ack 0si1 smbus1 interrupt flag. this bit is set by hardware under the conditions listed in table 28.3. si1 must be cleared by software. while si1 is set, scl1 is held low and the smbus1 is stalled. 0: no interrupt pending 1: interrupt pending 0: clear interrupt, and ini- tiate next state machine event. 1: force interrupt. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 202 preliminary rev. 0.71 28.4.5. hardware slave address recognition the smbus hardware has th e capability to automatica lly recognize incoming sl ave addresses and send an ack without software intervention. automatic slave address recognition is enabled by setting the ehack bit in register smb0adm to 1. this will enable both automatic slave address recognition and automatic hardware ack generation for received bytes (as a ma ster or slave). more detail on automatic hardware ack generation can be found in section 28.4.4.2. the registers used to define which address(es) ar e recognized by the hardware are the smbus slave address register and the smbus slave address mask re gister. a single address or range of addresses (including the general call address 0x00) can be specif ied using these two regist ers. the most-significant seven bits of the two regist ers are used to define wh ich addresses will be acked. a 1 in bit positions of the slave address mask slvm[6:0] enable a comparison between the received slave address and the hard- ware?s slave address slv[6:0] for those bits. a 0 in a bit of the sl ave address mask means that bit will be treated as a ?don?t care? for comparison purposes. in this case, either a 1 or a 0 value are acceptable on table 28.3. sources for hardware changes to smbncn bit set by hardware when: cleared by hardware when: mastern ? a start is generated. ? a stop is generated. ? arbitration is lost. txmoden ? start is generated. ? smbndat is written before the start of an smbus frame. ? a start is detected. ? arbitration is lost. ? smbndat is not written before the start of an smbus frame. stan ? a start followed by an address byte is received. ? must be cleared by software. ston ? a stop is detected while addressed as a slave. ? arbitration is lost due to a detected stop. ? a pending stop is generated. ackrqn ? a byte has been received and an ack response value is needed (only when hardware ack is not enabled). ? after each ack cycle. arblostn ? a repeated start is detected as a master when stan is low (unwanted repeated start). ? scln is sensed low while attempting to generate a stop or repeated start condition. ? sdan is sensed low wh ile transmitting a 1 (excluding ack bits). ? each time sin is cleared. ackn ? the incoming ack value is low (acknowledge). ? the incoming ack value is high (not acknowledge). sin ? a start has been generated. ? lost arbitration. ? a byte has been transmitted and an ack/ nack received. ? a byte has been received. ? a start or repeated start followed by a slave address + r/w has been received. ? a stop has been received. ? must be cleared by software. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 203 c8051f39x/37x the incoming slave address. additionally, if the gcn bi t in register smbnadr is set to 1, hardware will rec- ognize the general call address (0x00). table 28.4 shows some example parameter settings and the slave addresses that will be recognized by hardware under those conditions. sfr address = 0xd7; sfr page = 0 table 28.4. hardware address recognition examples (ehack = 1) hardware slave address slvn[6:0] slave address mask slvmn[6:0] gcn bit slave addresses recognized by hardware 0x34 0x7f 0 0x34 0x34 0x7f 1 0x34, 0x00 (general call) 0x34 0x7e 0 0x34, 0x35 0x34 0x7e 1 0x34, 0x35, 0x00 (general call) 0x70 0x73 0 0x70, 0x74, 0x78, 0x7c sfr definition 28.6. smb0adr: smbus0 slave address bit76543210 name slv0[6:0] gc0 type r/w r/w reset 00000000 bit name function 7:1 slv0[6:0] smbus hardware slave address. defines the smbus0 slave address(es) for automatic hardware acknowledgement. only address bits which have a 1 in the corresponding bit position in slvm0[6:0] are checked against the incoming address. this allows multiple addresses to be recognized. 0gc0 general call address enable. when hardware address recognition is enabled (ehack0 = 1), this bit will dete rmine whether the general call address (0x00) is also recognized by hardware. 0: general call ad dress is ignored. 1: general call address is recognized. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 204 preliminary rev. 0.71 sfr address = 0xe7; sfr page = 0 sfr definition 28.7. smb0adm : smbus0 slave address mask bit76543210 name slvm0[6:0] ehack0 type r/w r/w reset 11111110 bit name function 7:1 slvm0[6:0] smbus0 slave address mask. defines which bits of register smb0adr are compared with an incoming address byte, and which bits are ignored. any bit set to 1 in slvm0[6:0] enables comparisons with the corresponding bit in slv0[6:0]. bits set to 0 are ignored (can be either 0 or 1 in the incoming address). 0 ehack0 hardware acknowledge enable. enables hardware acknowled gement of slave address and received data bytes. 0: firmware must manually acknowledge all incoming address and data bytes. 1: automatic slave address recognition and hardware acknowledge is enabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 205 c8051f39x/37x sfr address = 0xd7; sfr page = f sfr definition 28.8. smb1adr: smbus1 slave address bit76543210 name slv1[6:0] gc1 type r/w r/w reset 00000000 bit name function 7:1 slv1[6:0] smbus1 hardware slave address. defines the smbus1 slave address(es) for automatic hardware acknowledgement. only address bits which have a 1 in the corresponding bit position in slvm1[6:0] are checked against the incoming address. this allows multiple addresses to be recognized. 0gc1 general call address enable. when hardware address recognition is enabled (ehack1 = 1), this bit will dete rmine whether the general call address (0x00) is also recognized by hardware. 0: general call ad dress is ignored. 1: general call address is recognized. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 206 preliminary rev. 0.71 sfr address = 0xe7; sfr page = f sfr definition 28.9. smb1adm : smbus1 slave address mask bit76543210 name slvm1[6:0] ehack1 type r/w r/w reset 11111110 bit name function 7:1 slvm1[6:0] smbus1 slave address mask. defines which bits of register smb1adr are compared with an incoming address byte, and which bits are ignored. any bit set to 1 in slvm1[6:0] enables comparisons with the corresponding bit in slv1[6:0]. bits set to 0 are ignored (can be either 0 or 1 in the incoming address). 0 ehack1 hardware acknowledge enable. enables hardware acknowled gement of slave address and received data bytes. 0: firmware must manually acknowledge all incoming address and data bytes. 1: automatic slave address recognition and hardware acknowledge is enabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 207 c8051f39x/37x 28.4.6. data register the smbus data register smbndat holds a byte of serial data to be transmitted or one that has just been received. software may safely read or write to the data register when the sin flag is set. software should not attempt to access the smbndat register when the smbus is ena bled and the sin flag is cleared to logic 0, as the interface may be in the process of sh ifting a byte of data into or out of the register. data in smbndat is always shifted ou t msb first. after a byte has been received, the first bit of received data is located at the msb of smbndat. while data is being shifted out, data on the bus is simultaneously being shifted in. smbndat always contains the last data byte present on the bus. in the event of lost arbi- tration, the transition from master transmitter to slav e receiver is made with the correct data or address in smbndat. sfr address = 0xc2; sfr page = 0 sfr definition 28.10. smb0dat: smbus data bit76543210 name smb0dat[7:0] type r/w reset 00000000 bit name function 7:0 smb0dat[7:0] smbus0 data. the smb0dat register contains a byte of data to be trans- mitted on the smbus0 serial interf ace or a byte that has just been received on the smbus0 serial interface. the cpu can read from or write to this register whenever the si0 serial interrupt flag (smb0cn.0) is set to logic 1. the serial data in the register remains stable as long as the si0 flag is set. when the si0 flag is no t set, the system may be in the process of shifting data in/out and the cpu should not attempt to access this register. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 208 preliminary rev. 0.71 sfr address = 0xc2; sfr page = f sfr definition 28.11. smb1dat: smbus data bit76543210 name smb1dat[7:0] type r/w reset 00000000 bit name function 7:0 smb1dat[7:0] smbus1 data. the smb1dat register contains a byte of data to be trans- mitted on the smbus1 serial interf ace or a byte that has just been received on the smbus1 serial interface. the cpu can read from or write to this register whenever the si1 serial interrupt flag (smb1cn.0) is set to logic 1. the serial data in the register remains stable as long as the si1 flag is set. when the si1 flag is no t set, the system may be in the process of shifting data in/out and the cpu should not attempt to access this register. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 209 c8051f39x/37x 28.5. smbus transfer modes the smbus interface may be configured to operate as master and/or slave. at any particular time, it will be operating in one of the following four modes: master transmitter, master receiver, slave transmitter, or slave receiver. the smbus interface enters master mo de any time a start is generated, and remains in master mode until it loses an arbitration or generates a stop. an smbus interrupt is generated at the end of all smbus byte frames. the position of the ack interrupt when operating as a receiver depends on whether hardware ack generation is enabled. as a receiver, the interrupt for an ack occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. as a transmitter, interrupts occur after the ack, regardless of w hether hardware ack generation is enabled or not. 28.5.1. write se quence (master) during a write sequence, an smbus ma ster writes data to a slave device . the master in th is transfer will be a transmitter during the address byte, and a transmitter during all data bytes. the smbus interface gener- ates the start condition and transmits the first byte containing the address of the target slave and the data direction bit. in this case the data direction bi t (r/w) will be logic 0 (write). the master then trans- mits one or more bytes of serial data. after each byte is transmitted, an acknowledge bit is generated by the slave. the transfer is ended wh en the sto bit is set and a stop is generated. the in terface will switch to master receiver mode if smb0 dat is not written following a master transmitter interrupt. figure 28.5 shows a typical master write sequence. two transmit data bytes are shown, though any number of bytes may be transmitted. notice that all of the ?data byte transferred? interrupts occur after the ack cycle in this mode, regardless of whether hard ware ack generation is enabled. figure 28.5. typical master write sequence a a a s w p data byte data byte sla s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 210 preliminary rev. 0.71 28.5.2. read sequence (master) during a read sequence, an smbus ma ster reads data from a slave devic e. the master in this transfer will be a transmitter during the address byte, and a receiv er during all data bytes. the smbus interface gener- ates the start condition and transmits the first byte containing the address of the target slave and the data direction bit. in this case the data directi on bit (r/w) will be logic 1 (read). serial data is then received from the slave on sda while the smbus outputs the serial clock. the slave transmits one or more bytes of serial data. if hardware ack generation is disabled, the ackrq is set to 1 and an interrupt is generated after each received byte. software must writ e the ack bit at that time to ack or nack the received byte. with hardware ack generation enab led, the smbus hardware will autom atically generate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. writing a 1 to the ack bit generates an ack; writing a 0 generates a nack. software should write a 0 to the ack bit for the last data transfer, to transmit a nack. the interface exits master receiver mode after the sto bit is set and a stop is generated. the in terface will switch to mast er transmitter mode if smb0dat is written while an active master receiver. figure 28.6 shows a typical master read sequence. two received data bytes are shown, though any number of bytes may be received. notice that the ?data byte transferred? interrupts occur at different places in the sequence, depending on whether hardware ack generation is enabled. the interrupt occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. figure 28.6. typical master read sequence data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 211 c8051f39x/37x 28.5.3. write sequence (slave) during a write sequence, an smbus ma ster writes data to a slave device. the slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode when a start followed by a slave address and direc- tion bit (write in this case) is received. if hardware ack generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ac krq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generation is enabled, th e hardware will apply the ac k for a slave address which matches the criteria set up by smb0adr and smb0adm. the inte rrupt will occur after the ack cycle. if the received slave address is ignore d (by software or hardware), slav e interrupts will be in hibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are received. if hardware ack generation is disabled, the ackrq is set to 1 and an interrupt is generated after each received byte. software must writ e the ack bit at that time to ack or nack the received byte. with hardware ack generation enab led, the smbus hardware will autom atically generate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. the interface exits slave receiver mode after receiving a stop. the in terface will switch to slave trans- mitter mode if smb0dat is written wh ile an active slave receiver. figu re 28.7 shows a typical slave write sequence. two received data bytes are shown, thou gh any number of bytes may be received. notice that the ?data byte transferred? interrupts occur at differ ent places in the sequence, depending on whether hard- ware ack generation is enabled. the interrupt occurs before the ack with hardware ack generation dis- abled, and after the ack when hardware ack generation is enabled. figure 28.7. typical slave write sequence p w sla s data byte data byte a a a s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 212 preliminary rev. 0.71 28.5.4. read se quence (slave) during a read sequence, an smbus ma ster reads data from a slave device. the slave in this transfer will be a receiver during the address byte, and a transm itter during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiv er mode (to receive the slave address) when a start followed by a slave address and direction bit (read in this case) is received. if hardware ack generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generat ion is enabled, the hardware will apply the ack for a slave address which matches the criteria set up by smb0adr and smb0adm. the interrupt will occur after the ack cycle. if the received slave address is ignore d (by software or hardware), slav e interrupts will be in hibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are trans- mitted. if the received slave address is acknowledged, data should be written to smb0dat to be transmit- ted. the interface enters slave transmitter mode, and transmits one or more bytes of data. after each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ack, smb0dat should be written with the next data byte. if the acknowle dge bit is a nack, smb0dat should not be written to before si is cleared (an error condition may be generated if smb0dat is written followin g a received nack while in slave transmitter mode ). the interface exits slave transmitter mode after receiving a stop. the interface will switch to slave receiver mode if smb0dat is not written following a slave transmitter interrupt. figure 28.8 shows a typical slave read sequence. two transmitted data bytes are shown, though any number of bytes may be transmitted. notice that all of the ?data byte transferred? interrupts occur after the ack cycle in this mode, regardless of whether hardware ack generation is enabled. figure 28.8. typical slave read sequence 28.6. smbus status decoding the current smbus status can be easily decoded usin g the smb0cn register. the appropriate actions to take in response to an smbus event depend on whether hardware slave address recognition and ack generation is enabled or disabled. table 28.5 descri bes the typical actions when hardware slave address recognition and ack generation is disabled. table 28. 6 describes the typical actions when hardware slave address recognition and ack generation is enabled. in the tables, status vector refers to the four upper bits of smb0cn: master, tx mode, sta, and sto. the shown response options are only the typ- ical responses; application-specific procedures are allo wed as long as they conform to the smbus specifi- cation. highlighted responses are allowed by hardwar e but do not conform to the smbus specification. p r sla s data byte data byte a n a s = start p = stop n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 213 c8051f39x/37x table 28.5. smbus status decoding: hardware ack disabled (ehack = 0) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was gener- ated. load slave address + r/w into smb0dat. 00x1100 1100 000 a master data or address byte was transmitted; nack received. set sta to restart transfer. 1 0 x 1110 abort transfer. 01x ? 001 a master data or address byte was transmitted; ack received. load next data byte into smb0dat. 00x1100 end transfer with stop. 0 1 x ? end transfer with stop and start another transfer. 11x ? send repeated start. 1 0 x 1110 switch to master receiver mode (clear si without writing new data to smb0dat). 0 0 x 1000 master receiver 1000 1 0 x a master data byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 1000 send nack to indi cate last byte, and send stop. 010 ? send nack to indi cate last byte, and send stop followed by start. 1101110 send ack followed by repeated start. 1011110 send nack to indi cate last byte, and send repeated start. 1001110 send ack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 1 1100 send nack and switch to mas- ter transmitter mode (write to smb0dat before clearing si). 0 0 0 1100 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 214 preliminary rev. 0.71 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting stop condition). 0 0 x 0001 001 a slave byte was transmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 0100 01x a slave byte was transmitted; error detected. no action required (expecting master to end transfer). 0 0 x 0001 0101 0 x x an illegal stop or bus error was detected while a slave transmission was in progress. clear sto. 00x ? slave receiver 0010 10x a slave address + r/w was received; ack requested. if write, ackno wledge received address 0 0 1 0000 if read, load smb0dat with data byte; ack received address 0 0 1 0100 nack received address. 0 0 0 ? 11x lost arbitration as master; slave address + r/w received; ack requested. if write, ackno wledge received address 0 0 1 0000 if read, load smb0dat with data byte; ack received address 0 0 1 0100 nack received address. 0 0 0 ? reschedule failed transfer; nack received address. 1001110 0001 00x a stop was detected while addressed as a slave trans- mitter or slave receiver. clear sto. 00x ? 11x lost arbitration while attempt- ing a stop. no action required (transfer complete/aborted). 000 ? 0000 1 0 x a slave byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 0000 nack received byte. 0 0 0 ? table 28.5. smbus status decoding: hardware ack disabled (ehack = 0) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 215 c8051f39x/37x bus error condition 0010 0 1 x lost arbitration while attempt- ing a repeated start. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0001 0 1 x lost arbitration due to a detected stop. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0000 1 1 x lost arbitration while transmit- ting a data byte as master. abort failed transfer. 0 0 0 ? reschedule failed transfer. 1 0 0 1110 table 28.6. smbus status decoding: hardware ack enabled (ehack = 1) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was gener- ated. load slave address + r/w into smb0dat. 00x1100 1100 000 a master data or address byte was transmitted; nack received. set sta to restart transfer. 1 0 x 1110 abort transfer. 01x ? 001 a master data or address byte was transmitted; ack received. load next data byte into smb0dat. 00x1100 end transfer with stop. 0 1 x ? end transfer with stop and start another transfer. 11x ? send repeated start. 1 0 x 1110 switch to master receiver mode (clear si without writing new data to smb0dat). set ack for initial data byte. 0 0 1 1000 table 28.5. smbus status decoding: hardware ack disabled (ehack = 0) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 216 preliminary rev. 0.71 master receiver 1000 001 a master data byte was received; ack sent. set ack for next data byte; read smb0dat. 0 0 1 1000 set nack to indicate next data byte as the last data byte; read smb0dat. 0 0 0 1000 initiate repeated start. 1 0 0 1110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100 000 a master data byte was received; nack sent (last byte). read smb0dat; send stop. 0 1 0 ? read smb0dat; send stop followed by start. 1101110 initiate repeated start. 1 0 0 1110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting stop condition). 0 0 x 0001 001 a slave byte was transmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 0100 01x a slave byte was transmitted; error detected. no action required (expecting master to end transfer). 0 0 x 0001 0101 0 x x an illegal stop or bus error was detected while a slave transmission was in progress. clear sto. 00x ? table 28.6. smbus status decoding: hard ware ack enabled (ehack = 1) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 217 c8051f39x/37x slave receiver 0010 00x a slave address + r/w was received; ack sent. if write, set ack for first data byte. 0 0 1 0000 if read, load smb0dat with data byte 0 0 x 0100 01x lost arbitration as master; slave address + r/w received; ack sent. if write, set ack for first data byte. 0 0 1 0000 if read, load smb0dat with data byte 0 0 x 0100 reschedule failed transfer 1 0 x 1110 0001 00x a stop was detected while addressed as a slave trans- mitter or slave receiver. clear sto. 00x ? 01x lost arbitration while attempt- ing a stop. no action required (transfer complete/aborted). 000 ? 0000 0 0 x a slave byte was received. set ack for next data byte; read smb0dat. 0 0 1 0000 set nack for next data byte; read smb0dat. 0 0 0 0000 bus error condition 0010 0 1 x lost arbitration while attempt- ing a repeated start. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0001 0 1 x lost arbitration due to a detected stop. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0000 0 1 x lost arbitration while transmit- ting a data byte as master. abort failed transfer. 0 0 x ? reschedule failed transfer. 10x1110 table 28.6. smbus status decoding: hard ware ack enabled (ehack = 1) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 218 preliminary rev. 0.71 29. uart0 uart0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 uart. enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in section ?29.1. enhanced baud rate generation? on page 219). received data buffering allows uart0 to start reception of a second incoming data byte be fore software has finished reading the previous data byte. uart0 has two associated sfrs: serial control regist er 0 (scon0) and serial data buffer 0 (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. writes to sbuf0 always access the transmit register. reads of sbuf0 always access the buffered receive register; it is not possible to read data from the transmit register. with uart0 interrupts enabled, an interrupt is generated each time a transmit is completed (ti0 is set in scon0), or a data byte has been received (ri0 is set in scon0). the uart0 interrupt flags are not cleared by hardware when the cpu vectors to the inte rrupt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart0 interrupt (transmit complete or receive complete). figure 29.1. uart0 block diagram uart baud rate generator ri scon ri ti rb8 tb8 ren mce smode tx control tx clock send sbuf (tx shift) start data write to sbuf crossbar tx shift zero detector tx irq set q d clr stop bit tb8 sfr bus serial port interrupt ti port i/o rx control start rx clock load sbuf shift 0x1ff rb8 rx irq input shift register (9 bits) load sbuf read sbuf sfr bus crossbar rx sbuf (rx latch) www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 219 c8051f39x/37x 29.1. enhanced ba ud rate generation the uart0 baud rate is generated by timer 1 in 8-bit auto-reload mode. the tx clock is generated by tl1; the rx clock is generated by a copy of tl1 (shown as rx timer in figure 29.2), which is not user- accessible. both tx and rx timer overflows are divided by two to generate the tx and rx baud rates. the rx timer runs when timer 1 is enabled, and uses the same reload value (th1). however, an rx timer reload is forced when a start condition is detected on the rx pin. this allows a receive to begin any time a start is detected, independent of the tx timer state. figure 29.2. uart0 baud rate logic timer 1 should be configured for mode 2, 8-bit auto -reload (see section ?31.1.3. mode 2: 8-bit counter/ timer with auto-reload? on page 245). the timer 1 relo ad value should be set so that overflows will occur at two times the desired uart baud rate frequency. note that timer 1 may be clocked by one of six sources: sysclk, sysclk/4, sysclk/12, sysclk/48, th e external oscillator cl ock/8, or an external input t1. for any given timer 1 clock source, the ua rt0 baud rate is determined by equation 29.1-a and equation 29.1-b. equation 29.1. uart0 baud rate where t1 clk is the frequency of the clock supplied to timer 1, and t1h is the high byte of timer 1 (reload value). timer 1 clock frequency is selected as descri bed in section ?31. timers? on page 240. a quick ref- erence for typical baud rates and system clock frequencies is given in table 29.1 through table 29.2. the internal oscillator may st ill generate the system cloc k when the external oscillator is driving timer 1. rx timer start detected overflow overflow th1 tl1 tx clock 2 rx clock 2 timer 1 uart uartbaudrate 1 2 -- - t1_overflow_rate ? = t1_overflow_rate t1 clk 256 th1 ? ------------ ------------- - = a) b) www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 220 preliminary rev. 0.71 29.2. operational modes uart0 provides standard asynchronous, full duplex communication. the uart mode (8-bit or 9-bit) is selected by the s0mode bit (sco n0.7). typical uart connection options are shown in figure 29.3. figure 29.3. uart interconnect diagram 29.2.1. 8-bit uart 8-bit uart mode uses a total of 10 bits per data byte: one start bit, eight data bits (lsb first), and one stop bit. data are transmitted lsb first from the tx0 pin and received at the rx0 pin. on receive, the eight data bits are stored in sbuf0 and the stop bit goes into rb80 (scon0.2). data transmission begins wh en software writes a data byte to th e sbuf0 register. the ti0 transmit inter- rupt flag (scon0.1) is set at the end of the transmi ssion (the beginning of the st op-bit time). data recep- tion can begin any time after the re n0 receive enable bit (scon0.4) is set to logic 1. after the stop bit is received, the data byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: ri0 must be logic 0, and if mce0 is logic 1, the stop bit must be logic 1. in the event of a receive data over- run, the first received 8 bits are la tched into the sbuf0 receive register and the following overrun data bits are lost. if these conditions are met, the eight bits of data is stored in sbuf0, the stop bit is stored in rb80 and the ri0 flag is set. if these conditio ns are not met, sbuf0 and rb80 will no t be loaded and the ri0 flag will not be set. an interrupt will occur if enabled when ei ther ti0 or ri0 is set. figure 29.4. 8-bit uart timing diagram or rs-232 c8051xxxx rs-232 level xltr tx rx c8051xxxx rx tx mcu rx tx d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 221 c8051f39x/37x 29.2.2. 9-bit uart 9-bit uart mode uses a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programma- ble ninth data bit, and a stop bit. the state of the nint h transmit data bit is determ ined by the value in tb80 (scon0.3), which is assigned by user software. it can be assigned the value of the parity flag (bit p in reg- ister psw) for error detection, or used in multiprocessor communications. on receive, the ninth data bit goes into rb80 (scon0.2) and the stop bit is ignored. data transmission begins when an instruction writes a data byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the tran smission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive enab le bit (scon0.4) is set to 1. after the stop bit is received, the data byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: (1) ri0 must be logic 0, and (2) if mce0 is logic 1, the 9th bit must be logic 1 (when mce0 is logic 0, the state of the ninth data bit is unimportant). if these co nditions are met, the eight bits of data are stored in sbuf0, the ninth bit is stored in rb80, and the ri0 fl ag is set to 1. if the above conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set to 1. a ua rt0 interrupt will occur if enabled when either ti0 or ri0 is set to 1. figure 29.5. 9-bit uart timing diagram d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 222 preliminary rev. 0.71 29.3. multiprocessor communications 9-bit uart mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). an address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. setting the mce0 bit (scon0.5) of a slave processor configures its uart such that when a stop bit is received, the uart will generate an inte rrupt only if the ninth bit is logic 1 (rb80 = 1) signifying an address byte has been received. in the ua rt interrupt handler, software will compare the receiv ed address with the slave's own assigned 8-bit addre ss. if the addresses match, the slav e will clear its mce0 bit to enable interrupts on the reception of the following data byte (s). slaves that weren't addressed leave their mce0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. once the entire message is rece ived, the addressed slave resets its mce0 bit to ignore all transmis- sions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is tem porarily reversed to enable half-duplex transmission between the original master and slave(s). figure 29.6. uart multi-processo r mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx v+ www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 223 c8051f39x/37x sfr address = 0x98; sfr page = all pages; bit-addressable sfr definition 29.1. scon0: serial port 0 control bit76543210 name s0mode mce0 ren0 tb80 rb80 ti0 ri0 type r/w r r/w r/w r/w r/w r/w r/w reset 01000000 bit name function 7s0mode serial port 0 operation mode. selects the uart0 operation mode. 0: 8-bit uart with variable baud rate. 1: 9-bit uart with variable baud rate. 6 unused unused. read = 1b, write = don?t care. 5mce0 multiprocessor communication enable. the function of this bit is dependent on the serial port 0 operation mode: mode 0: checks for valid stop bit. 0: logic level of stop bit is ignored. 1: ri0 will only be activated if stop bit is logic level 1. mode 1: multiprocessor communications enable. 0: logic level of ninth bit is ignored. 1: ri0 is set and an interrupt is gener ated only when the ninth bit is logic 1. 4ren0 receive enable. 0: uart0 reception disabled. 1: uart0 reception enabled. 3tb80 ninth transmission bit. the logic level of this bit will be sent as the ninth transmission bit in 9-bit uart mode (mode 1). unused in 8-bit mode (mode 0). 2rb80 ninth receive bit. rb80 is assigned the value of the stop bit in mode 0; it is assigned the value of the 9th data bit in mode 1. 1ti0 transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart0 (after the 8th bit in 8-bit uart mode, or at the beginning of the stop bit in 9-bit uart mode). when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by software. 0ri0 receive interrupt flag. set to 1 by hardware when a byte of da ta has been received by uart0 (set at the stop bit sampling time). when the uart0 interrupt is enabled, setting this bit to 1 causes the cp u to vector to the uart0 interrupt service routine. this bit must be cleared manually by software. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 224 preliminary rev. 0.71 sfr address = 0x99; sfr page = all pages sfr definition 29.2. sbuf0: seri al (uart0) port data buffer bit76543210 name sbuf0[7:0] type r/w reset 00000000 bit name function 7:0 sbuf0[7:0] serial data buffer bits 7?0 (msb?lsb). this sfr accesses two registers; a transmit shift register and a receive latch register. when data is written to sbuf0, it goes to the transmit shift register and is held for serial transmission. writing a byte to sbuf0 initiate s the transmission. a read of sbuf0 returns the contents of the receive latch. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 225 c8051f39x/37x table 29.1. timer settings for standard baud rates using the internal 49 mhz oscillator frequency: 49 mhz target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) sysclk from internal osc. 230400 ?0.32% 212 sysclk xx 2 10x96 115200 0.15% 426 sysclk xx 1 0x2b 57600 ?0.32% 848 sysclk/4 01 0 0x96 28800 0.15% 1704 sysclk/12 00 0 0xb9 9600 ?0.32% 5088 sysclk/48 00 0 0xcb 2400 0.15% 20448 sysclk/48 10 0 0x2b notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 31.1 . 2. x = don?t care. table 29.2. timer settings for standard baud rates using an external 22.1184 mhz oscillator frequency: 22.1184 mhz target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) sysclk from external osc. 230400 0.00% 96 sysclk xx 2 10xd0 115200 0.00% 192 sysclk xx 1 0xa0 57600 0.00% 384 sysclk xx 1 0x40 28800 0.00% 768 sysclk / 12 00 0 0xe0 14400 0.00% 1536 sysclk / 12 00 0 0xc0 9600 0.00% 2304 sysclk / 12 00 0 0xa0 2400 0.00% 9216 sysclk / 48 10 0 0xa0 1200 0.00% 18432 sysc lk / 48 10 0 0x40 sysclk from internal osc. 230400 0.00% 96 extclk / 8 11 0 0xfa 115200 0.00% 192 extclk / 8 11 0 0xf4 57600 0.00% 384 extclk / 8 11 0 0xe8 28800 0.00% 768 extclk / 8 11 0 0xd0 14400 0.00% 1536 extclk / 8 11 0 0xa0 9600 0.00% 2304 extclk / 8 11 0 0x70 notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 31.1 . 2. x = don?t care. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 226 preliminary rev. 0.71 30. enhanced serial pe ripheral interface (spi0) the enhanced serial peripheral interface (spi0) pr ovides access to a flexible, full-duplex synchronous serial bus. spi0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul- tiple masters and slaves on a single spi bus. the slave-select (nss) signal can be configured as an input to select spi0 in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the spi bus when more than one master attempts simultaneous data transfers. nss can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. additional gen- eral purpose port i/o pins can be used to se lect multiple slave dev ices in master mode. figure 30.1. spi block diagram sfr bus data path control sfr bus write spi0dat receive data buffer spi0dat 0 1 2 3 4 5 6 7 shift register spi control logic spi0ckr scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 spi0cfg spi0cn pin interface control pin control logic c r o s s b a r port i/o read spi0dat spi irq tx data rx data sck mosi miso nss transmit data buffer clock divide logic sysclk ckpha ckpol slvsel nssmd1 nssmd0 spibsy msten nssin srmt rxbmt spif wcol modf rxovrn txbmt spien www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 227 c8051f39x/37x 30.1. signal descriptions the four signals used by spi0 (mosi, miso, sck, nss) are described below. 30.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output fr om a master device and an input to slave devices. it is used to serially transfer data from the master to th e slave. this signal is an output when spi0 is operat- ing as a master and an input when spi0 is operating as a slave. data is transferred most-significant bit first. when configured as a master, mosi is driven by the msb of the shift register in both 3- and 4-wire mode. 30.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output fr om a slave device and an input to the master device. it is used to serially transfer data from the slave to the master. this signal is an input when spi0 is operat- ing as a master and an output when spi0 is operating as a slave. data is transferred most-significant bit first. the miso pin is placed in a high-impedance st ate when the spi module is disabled and when the spi operates in 4-wire mode as a slave that is not select ed. when acting as a slave in 3-wire mode, miso is always driven by the msb of the shift register. 30.1.3. serial clock (sck) the serial clock (sck) signal is an output from the ma ster device and an input to slave devices. it is used to synchronize the transfer of data between the mast er and slave on the mosi and miso lines. spi0 gen- erates this signal when operating as a master. the sck signal is ignored by a spi slave when the slave is not selected (nss = 1) in 4-wire slave mode. 30.1.4. slave select (nss) the function of the slave-select (nss) signal is dependent on the setting of the nssmd1 and nssmd0 bits in the spi0cn register. there are three possib le modes that can be selected with these bits: 1. nssmd[1:0] = 00: 3-wire master or 3-wire slave mode: spi0 operates in 3-wire mode, and nss is disabled. when operating as a slave device, spi0 is always selected in 3-wire mode. since no select signal is present, spi0 must be the only slave on th e bus in 3-wire mode. this is intended for point-to- point communication between a master and one slave. 2. nssmd[1:0] = 01: 4-wire slave or multi-master mode: spi0 operates in 4-wire mode, and nss is enabled as an input. when operating as a slave, nss selects the spi0 device. when operating as a master, a 1-to-0 transition of the nss signal disabl es the master function of spi0 so that multiple master devices can be used on the same spi bus. 3. nssmd[1:0] = 1x: 4-wire master mode: spi0 operat es in 4-wire mode, and nss is enabled as an output. the setting of nssmd0 dete rmines what logic level the nss pin will output. this configuration should only be used when operating spi0 as a master device. see figure 30.2, figure 30.3, and figure 30.4 for typica l connection diagrams of the various operational modes. note that the setting of nssmd bits affects the pinout of the device. when in 3-wire master or 3-wire slave mode, the nss pin will not be mapped by the crossbar. in all other modes, the nss signal will be mapped to a pin on the device. see section ?27. port input/output? on page 171 for general purpose port i/o and crossbar information. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 228 preliminary rev. 0.71 30.2. spi0 master mode operation a spi master device initiates all data transfers on a spi bus. spi0 is placed in master mode by setting the master enable flag (msten, spi0cn.6). writing a byte of data to the spi0 data register (spi0dat) when in master mode writes to the transmit buffer. if the spi shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. the spi0 master immediately shifts out the data serially on the mosi line while provid ing the serial clock on sck. the spi f (spi0cn.7) flag is set to logic 1 at the end of the transfer. if interrupts are enabl ed, an interrupt request is generated when the spif flag is set. while the spi0 master transf ers data to a slave on the mosi line, the addressed spi slave device simultaneously transfers the contents of its shift register to the spi master on the miso line in a full-duplex operation. therefore, the spif flag serves as both a transmit-complete and receive-data-ready flag. the data byte received from the slave is transferred msb- first into the master's shift register. when a byte is fully shifted into the register, it is moved to the re ceive buffer where it can be read by the processor by reading spi0dat. when configured as a master, spi0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. the default, multi-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in this mode, nss is an input to the device, and is used to disable the master spi0 when another ma ster is accessing the bus. when nss is pulled low in this mode, msten (spi0cn.6) and spien (spi0cn.0) ar e set to 0 to disable the spi master device, and a mode fault is generate d (modf, spi0cn.5 = 1). mode fault will gener ate an interrupt if enabled. spi0 must be manually re-enabled in soft ware under these circumstances. in multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. in multi-mas- ter mode, slave devices can be addressed individua lly (if needed) using general-purpose i/o pins. figure 30.2 shows a connection diagram between two master devices in multiple-mas ter mode. 3-wire single-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 0. in this mode, nss is not used, and is not mapped to an exte rnal port pin through the crossbar. any slave devices that must be addressed in this mode should be selected using general-purpose i/o pins. figure 30.3 shows a connection diagram between a master dev ice in 3-wire master mode and a slave device. 4-wire single-master mode is active when nssmd1 (spi0cn.3) = 1. in th is mode, nss is configured as an output pin, and can be used as a sl ave-select signal for a single spi dev ice. in this mode, the output value of nss is controlled (in software) with the bit n ssmd0 (spi0cn.2). additional slave devices can be addressed using general-purpose i/o pins. figure 30.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. figure 30.2. multiple-master mode connection diagram master device 2 master device 1 mosi miso sck miso mosi sck nss gpio nss gpio www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 229 c8051f39x/37x figure 30.3. 3-wire single master and 3-wire single slave mode connection diagram figure 30.4. 4-wire single master mode and 4-wire slave mode connection diagram 30.3. spi0 slave mode operation when spi0 is enabled and not confi gured as a master, it will operate as a spi slave. as a slave, bytes are shifted in through the mosi pin a nd out through the miso pin by a ma ster device controlling the sck sig- nal. a bit counter in the spi0 logic counts sck edges . when 8 bits have been shifted through the shift reg- ister, the spif flag is set to logic 1, and the byte is copied into the receive buffer. data is read from the receive buffer by reading spi0dat. a slave device cannot initiate transfers. data to be transferred to the master device is pre-loaded into the shift register by writing to spi0dat. writes to spi0dat are double- buffered, and are placed in the transmit buffer first. if the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. when the sh ift register already contains data, the spi will load the shift register wi th the transmit buffer?s contents af ter the last sck edg e of the next (or current) spi transfer. when configured as a slave, spi0 can be configured for 4-wire or 3-wire operation. the default, 4-wire slave mode, is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in 4-wire mode, the nss signal is routed to a port pin and configured as a digital input. spi0 is enabled when nss is logic 0, and disabled when nss is logic 1. the bit counter is reset on a falling edge of n ss. note that the nss sig- nal must be driven low at least 2 system clocks before the first active edge of sck for each byte transfer. figure 30.4 shows a connection diagram between tw o slave devices in 4-wire slave mode and a master device. the 3-wire slave mode is active when nssmd1 ( spi0cn.3) = 0 and nssmd0 ( spi0cn.2) = 0. nss is not used in this mode, and is not mapped to an external port pin through the crossbar. since there is no way of slave device master device mosi miso sck miso mosi sck slave device master device mosi miso sck miso mosi sck nss nss gpio slave device mosi miso sck nss www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 230 preliminary rev. 0.71 uniquely addressing the device in 3-wire slave mode , spi0 must be the only slav e device present on the bus. it is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. th e bit counter can only be reset by disabling and re- enabling spi0 with the spien bit. figure 30.3 shows a connection diagram between a slave device in 3- wire slave mode and a master device. 30.4. spi0 interrupt sources when spi0 interrupts are e nabled, the following four flags will gener ate an interrupt when they are set to logic 1: all of the following bits must be cleared by software. ? the spi interrupt flag, spif (spi0cn.7) is set to logic 1 at the end of each byte transfer. this flag can occur in all spi0 modes. ? the write collision flag, wcol (spi0cn.6) is set to logic 1 if a write to spi0dat is attempted when the transmit buffer has not been emptied to the spi shift register. when this occurs, the write to spi0dat will be ignored, and the tr ansmit buffer will not be writte n.this flag can occur in all spi0 modes. ? the mode fault flag modf (spi0cn.5) is set to logi c 1 when spi0 is configured as a master, and for multi-master mode and the nss pin is pulled low. when a mode fault occurs, the msten and spien bits in spi0cn are set to logic 0 to disable spi0 an d allow another master device to access the bus. ? the receive overrun flag rxovrn (spi0cn.4) is se t to logic 1 when configured as a slave, and a transfer is completed and the rece ive buffer still holds an unread byte from a prev ious transfer. the new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. the data byte which caused the overrun is lost. 30.5. serial clock phase and polarity four combinations of serial clock phase and polarity can be selected using the clock control bits in the spi0 configuration register (spi0c fg). the ckpha bit ( spi0cfg.5) selects one of two clock phases (edge used to latch the data). the ckpol bit (spi0cfg.4) selects between an active-high or active-low clock. both master and slave devices must be config ured to use the same clock phase and polarity. spi0 should be disabled (by clearing the spien bit, spi0 cn.0) when changing the clock phase or polarity. the clock and data line relationships for master mode are shown in figure 30.5. for slave mode, the clock and data relationships are shown in figure 30.6 and figure 30.7. note that ckpha should be set to 0 on both the master and slave spi when communicat ing between two silicon labs c8051 devices. the spi0 clock rate register (spi 0ckr) as shown in sfr definition 30.3 controls the master mode serial clock frequency. this register is ignored wh en operating in slave mode. when the spi is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 mhz, whichever is slower. when the spi is configured as a sl ave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency , provided that the master issues sck, nss (in 4- wire slave mode), and the serial input data synchrono usly with the slave?s system clock. if the master issues sck, nss, and t he serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. in the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the spi slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. this is provided that the master i ssues sck, nss, and the serial inpu t data synchronously with the slave?s system clock. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 231 c8051f39x/37x figure 30.5. master mode data/clock timing figure 30.6. slave mode data/clock timing (ckpha = 0) sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso/mosi nss (must remain high in multi-master mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi sck (ckpol=0, ckpha=0) sck (ckpol=1, ckpha=0) www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 232 preliminary rev. 0.71 figure 30.7. slave mode data/clock timing (ckpha = 1) 30.6. spi special function registers spi0 is accessed and controlled through four special function registers in the system controller: spi0cn control register, spi0dat data register, spi0cf g configuration register, and spi0ckr clock rate register. the four special function registers related to the operation of the spi0 bus are described in the following figures. sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 233 c8051f39x/37x sfr address = 0xa1; sfr page = all pages sfr definition 30.1. spi0c fg: spi0 configuration bit7654321 0 name spibsy msten ckpha ckpol slvsel nssin srmt rxbmt type r r/w r/w r/w r r r r reset 0000011 1 bit name function 7 spibsy spi busy. this bit is set to logic 1 when a spi transfer is in progress (master or slave mode). 6 msten master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode. operate as a master. 5ckpha spi0 clock phase. 0: data centered on first edge of sck period. * 1: data centered on second edge of sck period. * 4 ckpol spi0 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. 3 slvsel slave selected flag. this bit is set to logic 1 whenever the ns s pin is low indicating spi0 is the selected slave. it is cleared to logic 0 when nss is hi gh (slave not selected). this bit does not indicate the instantaneous value at the nss pin, but rather a de-glitched version of the pin input. 2 nssin nss instantaneous pin input. this bit mimics the instantaneous value that is present on the nss port pin at the time that the register is read . this input is not de-glitched. 1srmt shift register empty (val id in slave mode only). this bit will be set to logic 1 when all data has been transferred in /out of the shift reg- ister, and there is no new information available to read from the transmit buffer or write to the receive buffer. it returns to logic 0 when a data byte is transferred to the shift register from the transm it buffer or by a transition on sck. srmt = 1 when in master mode. 0 rxbmt receive buffer empty (valid in slave mode only). this bit will be set to logic 1 when the receiv e buffer has been r ead and contains no new information. if th ere is new information available in the receive buffer that has not been read, this bit will return to lo gic 0. rxbmt = 1 when in master mode. note: in slave mode, data on mosi is sampled in the center of each data bit. in master mode, data on miso is sampled one sysclk before t he end of each data bit, to provide ma ximum settling time fo r the slave device. see table 30.1 for timing parameters. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 234 preliminary rev. 0.71 sfr address = 0xf8; sfr page = all pages; bit-addressable sfr definition 30.2. spi0cn: spi0 control bit7654321 0 name spif wcol modf rxovrn nssmd[1:0] txbmt spien type r/w r/w r/w r/w r/w r r/w reset 0000011 0 bit name function 7 spif spi0 interrupt flag. this bit is set to logic 1 by hardware at the end of a data transfer. if spi interrupts are enabled, an interrupt will be generated. this bit is no t automatically cleared by hardware, and must be cleared by software. 6wcol write collision flag. this bit is set to logic 1 if a write to spi 0dat is attempted when txbmt is 0. when this occurs, the write to spi0dat will be ignored, and the transm it buffer will not be written. if spi interrupts ar e enabled, an interrupt will be generated. this bit is not automatically cleared by hardware, and must be cleared by software. 5modf mode fault flag. this bit is set to logic 1 by hardware wh en a master mode collision is detected (nss is low, msten = 1, and nssmd[1:0] = 01). if spi interrupts are enabled, an inter- rupt will be generated. this bit is not au tomatically cleared by hardware, and must be cleared by software. 4rxovrn receive overrun flag (valid in slave mode only). this bit is set to logic 1 by hardware wh en the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the spi0 shift register. if spi interrupts are en abled, an inte rrupt will be generated. this bit is not automatically cleared by hardware, and must be cleared by software. 3:2 nssmd[1:0] slave select mode. selects between the follo wing nss operation modes: (see section 30.2 and section 30.3). 00: 3-wire slave or 3-wire master mode. nss signal is not routed to a port pin. 01: 4-wire slave or multi-master mode (d efault). nss is an input to the device. 1x: 4-wire single-master mode. nss signal is mapped as an output from the device and will assume the value of nssmd0. 1 txbmt transmit buffer empty. this bit will be set to logic 0 when new data has been wri tten to the transmit buffer. when data in the transmit buffer is transf erred to the spi shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. 0 spien spi0 enable. 0: spi disabled. 1: spi enabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 235 c8051f39x/37x sfr address = 0xa2; sfr page = all pages sfr definition 30.3. spi0ckr: spi0 clock rate bit7654321 0 name scr[7:0] type r/w reset 0000000 0 bit name function 7:0 scr[7:0] spi0 clock rate. these bits determine the frequency of the sck output when the spi0 module is configured for master mode operation. the sck clock frequency is a divided version of the system clock, and is given in the following equation, where sysclk is the system clock frequency and spi0ckr is the 8-bit value held in the spi0ckr register. for 0 <= spi0ckr <= 255 example: if sysclk = 2 mhz and spi0ckr = 0x04, f sck sysclk 2 spi0ckr[7:0] 1 + ?? ? ------------------- ---------------------- ----------------- - = f sck 2000000 241 + ?? ? --------------- ----------- = f sck 200 khz = www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 236 preliminary rev. 0.71 sfr address = 0xa3; sfr page = all pages figure 30.8. spi master timing (ckpha = 0) sfr definition 30.4. spi0dat: spi0 data bit7654321 0 name spi0dat[7:0] type r/w reset 0000000 0 bit name function 7:0 spi0dat[7:0] spi0 transmit and receive data. the spi0dat register is used to transmit and receive spi0 data. writing data to spi0dat places the data into the trans- mit buffer and initiates a transfer when in master mode. a read of spi0dat returns the contents of the receive buffer. sck* t mckh t mckl mosi t mis miso * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mih www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 237 c8051f39x/37x figure 30.9. spi master timing (ckpha = 1) figure 30.10. spi slave timing (ckpha = 0) sck* t mckh t mckl miso t mih mosi * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mis sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t sez t sdz www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 238 preliminary rev. 0.71 figure 30.11. spi slave timing (ckpha = 1) sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t slh t sez t sdz www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 239 c8051f39x/37x table 30.1. spi slave timing parameters parameter description min max units master mode timing (see figure 30.8 and figure 30.9) t mckh sck high time 1 x t sysclk ?ns t mckl sck low time 1 x t sysclk ?ns t mis miso valid to sck shift edge 1 x t sysclk + 20 ? ns t mih sck shift edge to miso change 0 ? ns slave mode timing (see figure 30.10 and figure 30.11) t se nss falling to first sck edge 2 x t sysclk ?ns t sd last sck edge to nss rising 2 x t sysclk ?ns t sez nss falling to miso valid ? 4 x t sysclk ns t sdz nss rising to miso high-z ? 4 x t sysclk ns t ckh sck high time 5 x t sysclk ?ns t ckl sck low time 5 x t sysclk ?ns t sis mosi valid to sck sample edge 2 x t sysclk ?ns t sih sck sample edge to mosi change 2 x t sysclk ?ns t soh sck shift edge to miso change ? 4 x t sysclk ns t slh last sck edge to miso change (ckpha = 1 only) 6xt sysclk 8xt sysclk ns note: t sysclk is equal to one per iod of the device syst em clock (sysclk). www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 240 preliminary rev. 0.71 31. timers each mcu includes six counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and four are 16-bit auto-reload timer for use with the smbus or for general purpose use. these timers can be used to measure time intervals, count external events and generate periodic interrupt requests. timer 0 and timer 1 are nearly identical and have four primary modes of operation. timer 2, 3, 4, and 5 offer 16-bit and split 8-bit timer functionality with auto-reload. timers 0 and 1 may be clocked by one of five source s, determined by the timer mode select bits (t1m ? t0m) and the clock scale bits (sca1 ? sca0). the clock scale bits define a pre-scaled clock from which timer 0 and/or timer 1 may be clocked (see sfr definition 31.1 for pre-scaled clock selection). timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. timer 2, 3, 4, and 5 may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided by 8. timer 0 and timer 1 may also be operated as counte rs. when functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (t0 or t1). events with a fre- quency of up to one-fourth the system clock frequency can be counted. the input signal need not be peri- odic, but it should be held at a gi ven level for at least two full system clock cycles to ensure the level is properly sampled. timer 0 and timer 1 modes: timer 2, 3, 4, and 5 modes: 13-bit counter/timer 16-bit timer with auto-reload 16-bit counter/timer 8-bit counter/timer with auto-reload two 8-bit timers with auto-reload two 8-bit counter/timers (timer 0 only) www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 241 c8051f39x/37x sfr address = 0x8e; sfr page = all pages sfr definition 31.1. ckcon: clock control bit76543210 name t3mh t3ml t2mh t2ml t1m t0m sca[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7t3mh timer 3 high byte clock select. selects the clock supplied to the timer 3 high byte (split 8-bit timer mode only). 0: timer 3 high byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 high byte uses the system clock. 6t3ml timer 3 low byte clock select. selects the clock supplied to timer 3. selects the clock supplied to the lower 8- bit timer in split 8-bit timer mode. 0: timer 3 low byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 low byte uses the system clock. 5t2mh timer 2 high byte clock select. selects the clock supplied to the timer 2 high byte (split 8-bit timer mode only). 0: timer 2 high byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 high byte uses the system clock. 4t2ml timer 2 low byte clock select. selects the clock supplied to timer 2. if time r 2 is configured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: timer 2 low byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 low byte uses the system clock. 3t1 timer 1 clock select. selects the clock source supplied to timer 1. ignored when c/t1 is set to 1. 0: timer 1 uses the clock defined by the prescale bits sca[1:0]. 1: timer 1 uses the system clock. 2t0 timer 0 clock select. selects the clock source su pplied to timer 0. ignored when c/t0 is set to 1. 0: counter/timer 0 uses the clock defin ed by the prescale bits sca[1:0]. 1: counter/timer 0 uses the system clock. 1:0 sca[1:0] timer 0/1 prescale bits. these bits control the timer 0/1 clock prescaler: 00: system clock divided by 12 01: system clock divided by 4 10: system clock divided by 48 11: external clock divided by 8 (synchronized with the system clock) www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 242 preliminary rev. 0.71 sfr address = 0xf4; sfr page = all pages sfr definition 31.2. ckcon1: clock control 1 bit76543210 name t5mh t5ml t4mh t4ml type rrrrr/wr/wr/wr/w reset 00000000 bit name function 7:4 unused read = 0000b; write = don?t care 3t5mh timer 5 high byte clock select. selects the clock supplied to the timer 5 high byte (split 8-bit timer mode only). 0: timer 5 high byte uses the clock defined by the t5xclk bit in tmr5cn. 1: timer 5 high byte uses the system clock. 2t5ml timer 5 low byte clock select. selects the clock supplied to time r 5. selects the clock supplied to the lower 8-bit timer in split 8-bit timer mode. 0: timer 5 low byte uses the clock defined by the t5xclk bit in tmr5cn. 1: timer 5 low byte uses the system clock. 1t4mh timer 4 high byte clock select. selects the clock supplied to the timer 4 high byte (split 8-bit timer mode only). 0: timer 4 high byte uses the clock defined by the t4xclk bit in tmr4cn. 1: timer 4 high byte uses the system clock. 0t4ml timer 4 low byte clock select. selects the clock supplied to timer 4 . if timer 4 is configured in split 8-bit timer mode, this bit selects th e clock supplied to the lower 8-bit timer. 0: timer 4 low byte uses the clock defined by the t4xclk bit in tmr4cn. 1: timer 4 low byte uses the system clock. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 243 c8051f39x/37x 31.1. timer 0 and timer 1 each timer is implemented as a 16-bit register acce ssed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the counter/timer cont rol register (tcon) is used to enable timer 0 and timer 1 as well as indicate status. timer 0 interrupts can be enabled by setting the et0 bit in the ie regis- ter (section ?20.2. interrupt register descriptions? on page 118); timer 1 interrupts can be enabled by set- ting the et1 bit in the ie register (section ?20. 2. interrupt register descriptions? on page 118). both counter/timers operate in one of four primary m odes selected by setting the mode select bits t1m1 ? t0m0 in the counter/timer mode register (tmod). each timer can be configured independently. each operating mode is described below. 31.1.1. mode 0: 13 -bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration and operation of timer 0. however, both timers operate identically, and timer 1 is configured in the same manner as described for timer 0. the th0 register holds the eight msbs of the 13-bit c ounter/timer. tl0 holds the five lsbs in bit positions tl0.4 ? tl0.0. the three upper bits of tl0 (tl0.7 ? tl0.5) are indeterminate a nd should be masked out or ignored when reading. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf0 in tcon is set and an interrupt will occur if timer 0 interrupts are enabled. the c/t0 bit in the tmod register selects the counte r/timer's clock source. when c/t0 is set to logic 1, high-to-low transitions at the selected timer 0 input pi n (t0) increment the timer register (refer to section ?27.3. priority crossbar decoder? on page 176 for information on selecting and configuring external i/o pins). clearing c/t selects the clock defined by the t0 m bit in register ckcon. when t0m is set, timer 0 is clocked by the system clock. when t0m is cleared, timer 0 is clocke d by the source selected by the clock scale bits in ckcon (see sfr definition 31.1). setting the tr0 bit (tcon.4) enables the timer when eit her gate0 in the tmod register is logic 0 or the input signal int0 is active as defined by bit in0pl in regi ster it01cf (see sfr definition 20.10). setting gate0 to 1 allows the timer to be controlled by the external input signal int0 (see section ?20.2. interrupt register descriptions? on page 118), facilitating pulse width measurements setting tr0 does not force the timer to reset. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. timer 1 is configured and controlled using the releva nt tcon and tmod bits just as with timer 0. the input signal int0 is used with timer 1; the /int1 polarity is defined by bit in1pl in register it01cf (see sfr definition 20.10). tr0 gate0 int0 counter/timer 0 x x disabled 1 0 x enabled 1 1 0 disabled 1 1 1 enabled note: x = don't care www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 244 preliminary rev. 0.71 figure 31.1. t0 mode 0 block diagram 31.1.2. mode 1: 16 -bit counter/timer mode 1 operation is the same as mode 0, except that the counter/timer registers use all 16 bits. the coun- ter/timers are enabled and configured in mode 1 in the same manner as for mode 0. tclk tl0 (5 bits) th0 (8 bits) tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tr0 0 1 0 1 sysclk pre-scaled clock tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 /int0 t0 crossbar it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 in0pl xor t0m www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 245 c8051f39x/37x 31.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8-bi t counter/timers with auto matic reload of the start value. tl0 holds the count and th0 holds the reload va lue. when the counter in tl0 overflows from all ones to 0x00, the timer overflow fl ag tf0 in the tcon register is set and the counter in tl0 is reloaded from th0. if timer 0 interrupts ar e enabled, an interr upt will occur when the tf0 flag is set. the reload value in th0 is not changed. tl0 must be initialized to the desired value before enabling the timer for the first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit (tcon.4) enables the timer when either gate0 in the tmod regi ster is logic 0 or when the input signal int0 is active as defined by bit in0pl in regist er it01cf (see section ?20.3. external interrupts int0 and int1? on page 126 for details on the external input signals int0 and int1 ). figure 31.2. t0 mode 2 block diagram tclk tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tl0 (8 bits) reload th0 (8 bits) 0 1 0 1 sysclk pre-scaled clock it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 tr0 gate0 in0pl xor /int0 t0 crossbar t0m www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 246 preliminary rev. 0.71 31.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8- bit counter/timers held in tl0 and th0. the counter/ timer in tl0 is controlled using the timer 0 control/st atus bits in tcon and tmod: tr0, c/t0, gate0 and tf0. tl0 can use eit her the system clock or an external input si gnal as its timebase. the th0 register is restricted to a timer function sourced by the system clock or prescaled clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the timer 1 ov erflow flag tf1 on overflow and thus controls the timer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is op erating in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud rates for the smbus and/or uart, and/or initiate adc conversions. while timer 0 is operating in mode 3, timer 1 run control is handled through its mode set- tings. to run timer 1 while timer 0 is in mode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, configure it for mode 3. figure 31.3. t0 mode 3 block diagram tl0 (8 bits) tmod 0 1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt 0 1 sysclk pre-scaled clock tr1 th0 (8 bits) t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tr0 gate0 in0pl xor /int0 t0 crossbar t0m www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 247 c8051f39x/37x sfr address = 0x88; sfr page = all pages; bit-addressable sfr definition 31.3. tcon: timer control bit76543210 name tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 tf1 timer 1 overflow flag. set to 1 by hardware when timer 1 overflows. this flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 1 interrupt service routine. 6tr1 timer 1 run control. timer 1 is enabled by setting this bit to 1. 5 tf0 timer 0 overflow flag. set to 1 by hardware when timer 0 overflows. this flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 0 interrupt service routine. 4tr0 timer 0 run control. timer 0 is enabled by setting this bit to 1. 3ie1 external interrupt 1. this flag is set by hardware when an edge/level of type defined by it1 is detected. it can be cleared by software but is automat ically cleared when the cpu vectors to the external interrupt 1 service routine in edge-triggered mode. 2it1 interrupt 1 type select. this bit selects whether t he configured /int1 interrup t will be edge or level sensi- tive. /int1 is configured active low or hi gh by the in1pl bit in the it01cf register (see sfr definition 20.10). 0: /int1 is le vel triggered. 1: /int1 is edge triggered. 1ie0 external interrupt 0. this flag is set by hardware when an edge/level of type defined by it1 is detected. it can be cleared by software but is automat ically cleared when the cpu vectors to the external interrupt 0 service routine in edge-triggered mode. 0it0 interrupt 0 type select. this bit selects whether the configured int0 interrupt will be e dge or level sensi- tive. int0 is configured active low or high by the in0pl bit in register it01cf (see sfr definition 20.10). 0: int0 is level triggered. 1: int0 is edge triggered. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 248 preliminary rev. 0.71 sfr address = 0x89; sfr page = all pages sfr definition 31.4. tmod: timer mode bit76543210 name gate1 c/t1 t1m[1:0] gate0 c/t0 t0m[1:0] type r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7gate1 timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of int1 logic level. 1: timer 1 enabled only when tr1 = 1 and int1 is active as defined by bit in1pl in register it01cf (see sfr definition 20.10). 6c/t1 counter/timer 1 select. 0: timer: timer 1 incremented by clock defined by t1m bit in register ckcon. 1: counter: timer 1 incremented by high-t o-low transitions on external pin (t1). 5:4 t1m[1:0] timer 1 mode select. these bits select the timer 1 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, timer 1 inactive 3gate0 timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of int0 logic level. 1: timer 0 enabled only when tr0 = 1 and int0 is active as defined by bit in0pl in register it01cf (see sfr definition 20.10). 2c/t0 counter/timer 0 select. 0: timer: timer 0 incremented by clock defined by t0m bit in register ckcon. 1: counter: timer 0 incremented by high-t o-low transitions on external pin (t0). 1:0 t0m[1:0] timer 0 mode select. these bits select the timer 0 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, two 8-bit counter/timers www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 249 c8051f39x/37x sfr address = 0x8a; sfr page = all pages sfr address = 0x8b; sfr page = all pages sfr definition 31.5. tl0: timer 0 low byte bit76543210 name tl0[7:0] type r/w reset 00000000 bit name function 7:0 tl0[7:0] timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0. sfr definition 31.6. tl1: timer 1 low byte bit76543210 name tl1[7:0] type r/w reset 00000000 bit name function 7:0 tl1[7:0] timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 250 preliminary rev. 0.71 sfr address = 0x8c; sfr page = all pages sfr address = 0x8d; sfr page = all pages sfr definition 31.7. th0 : timer 0 high byte bit76543210 name th0[7:0] type r/w reset 00000000 bit name function 7:0 th0[7:0] timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. sfr definition 31.8. th1 : timer 1 high byte bit76543210 name th1[7:0] type r/w reset 00000000 bit name function 7:0 th1[7:0] timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 251 c8051f39x/37x 31.2. timer 2 timer 2 is a 16-bit timer formed by two 8-bit sfrs: tmr2l (low byte) and tmr2h (high byte). timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t2split bit (tmr2cn.3) defines the timer 2 operation mode. timer 2 may be clocked by the system clock, the syst em clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives t he system clock while timer 2 (and/or the pca) is clocked by an external preci- sion oscillator. note that the external oscillator source divided by 8 is synchronized with the system clock. 31.2.1. 16-bit time r with auto-reload when t2split (tmr2cn.3) is zero, timer 2 operates as a 16-bit timer with au to-reload. timer 2 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16 -bit value in the timer 2 reload registers (tmr2rlh and tmr2rll) is loaded in to the timer 2 register as shown in figure 31.4, and the timer 2 high byte overflow flag (tmr2cn.7) is set. if timer 2 interrupts are enabled (if ie.5 is set), an interrupt will be generated on each timer 2 overflow. additionally , if timer 2 interrupts are enabled and the tf2len bit is set (tmr2cn. 5), an interr upt will be generated each time the lower 8 bits (tmr2l) overflow from 0xff to 0x00. figure 31.4. timer 2 16-bit mode block diagram external clock / 8 sysclk / 12 sysclk tmr2l tmr2h tmr2rll tmr2rlh reload tclk 0 1 tr2 tmr2cn t2split tf2cen tf2l tf2h t2xclk tr2 0 1 t2xclk interrupt tf2len to adc, smbus to smbus tl2 overflow ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 252 preliminary rev. 0.71 31.2.2. 8-bit timers with auto-reload when t2split is set, timer 2 operates as two 8-bi t timers (tmr2h and tmr2l). both 8-bit timers oper- ate in auto-reload mode as shown in figure 31.5. tmr2rll holds the reload value for tmr2l; tmr2rlh holds the reload value for tmr2h. the tr2 bit in tmr2cn handles the run control for tmr2h. tmr2l is always running when configured for 8-bit mode. each 8-bit timer may be c onfigured to use sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 2 clock select bits (t2mh and t2ml in ckcon) select either sysclk or the clock defined by the timer 2 external cloc k select bit (t2xclk in tmr2cn), as follows: the tf2h bit is set when tmr2h overflows from 0xff to 0x00; the tf2l bit is set when tmr2l overflows from 0xff to 0x00. when timer 2 interrupts are enabled (ie.5), an interrupt is generated each time tmr2h overflows. if timer 2 interrupts are enabled an d tf2len (tmr2cn.5) is set, an interrupt is gener- ated each time either tmr2l or tmr2h overflows. when tf2len is enabled, software must check the tf2h and tf2l flags to determine the source of the timer 2 interrupt. the tf2h and tf2l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 31.5. timer 2 8-bit mode block diagram t2mh t2xclk tmr2h clock source t2ml t2xclk tmr2l clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr2 external clock / 8 sysclk / 12 0 1 t2xclk 1 0 tmr2h tmr2rlh reload reload tclk tmr2l tmr2rll interrupt tmr2cn t2split tf2cen tf2len tf2l tf2h t2xclk tr2 to adc, smbus to smbus ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 253 c8051f39x/37x 31.2.3. low-frequency oscillator (lfo) capture mode the low-frequency oscillator captur e mode allows the lfo clock to be measured against the system clock or an external oscillator so urce. timer 2 can be clocked from t he system clock, the system clock divided by 12, or the external oscillator divided by 8, depending on the t2 ml (ckcon.4), and t2xclk settings. setting tf2cen to 1 enables the lfo capture mode for timer 2. in this mode, t2split should be set to 0, as the full 16-bit timer is used . upon a falling edge of th e low-frequency oscillator, the contents of timer 2 (tmr2h:tmr2l) are loaded into the timer 2 rel oad registers (tmr2rlh:tmr2rll) and the tf2h flag is set. by recording the difference between two su ccessive timer capture valu es, the lfo clock frequency can be determined with respect to the timer 2 clock. the timer 2 clock should be much faster than the lfo to achieve an accurate reading. figure 31.6. timer 2 low-frequency oscillation capture mode block diagram external clock / 8 sysclk / 12 sysclk 0 1 0 1 t2xclk ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr2l tmr2h tclk tr2 tmr2rll tmr2rlh capture low-frequency oscillator tmr2cn t2split tf2cen tf2l tf2h t2xclk tr2 tf2len tf2cen interrupt www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 254 preliminary rev. 0.71 sfr address = 0xc8; sfr pa ge = 0; bit-addressable sfr definition 31.9. tmr 2cn: timer 2 control bit76543210 name tf2h tf2l tf2len tf2cen t2split tr2 t2xclk type r/w r/w r/w r/w r/w r/w r r/w reset 00000000 bit name function 7 tf2h timer 2 high byte overflow flag. set by hardware when the timer 2 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 2 over flows from 0xffff to 0x0000. when the timer 2 interrupt is enabled, setting this bi t causes the cpu to vector to the timer 2 interrupt service routine. this bit is not automatically cleared by hardware. 6 tf2l timer 2 low byte overflow flag. set by hardware when the timer 2 low byte overflows from 0xff to 0x00. tf2l will be set when the low byte overflows regardless of the timer 2 mode. this bit is not auto- matically cleared by hardware. 5tf2len timer 2 low byte interrupt enable. when set to 1, this bit enables timer 2 low byte interrupts. if ti mer 2 interrupts are also enabled, an interrupt w ill be generated when the low byte of timer 2 overflows. 4tf2cen timer 2 low-frequency oscillator capture enable. when set to 1, this bit enables timer 2 low-frequency oscilla tor capture mode. if tf2cen is set and timer 2 inte rrupts are enabled, an interrupt will be generated on a falling edge of the low- frequency oscillator ou tput, and the current 16 -bit timer value in tmr2h:tmr2l will be copi ed to tmr2rlh:tmr2rll. 3t2split timer 2 split mode enable. when this bit is set, timer 2 operates as two 8-bit timers with auto-reload. 0: timer 2 operates in 16-bit auto-reload mode. 1: timer 2 operates as two 8-bit auto-reload timers. 2tr2 timer 2 run control. timer 2 is enabled by setting th is bit to 1. in 8-bit mode , this bit enables/disables tmr2h only; tmr2l is alwa ys enabled in split mode. 1 unused unused. read = 0b; write = don?t care 0t2xclk timer 2 external clock select. this bit selects the external clock source for timer 2. if timer 2 is in 8-bit mode, this bit selects the external oscillator clock source for bo th timer bytes. however, the timer 2 clock select bits (t2mh and t2ml in regi ster ckcon) may still be used to select between the external clock and the system clock for either timer. 0: timer 2 clock is the system clock divided by 12. 1: timer 2 clock is the ex ternal clock divi ded by 8 (synchronized with sysclk). www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 255 c8051f39x/37x sfr address = 0xca; sfr page = 0 sfr address = 0xcb; sfr page = 0 sfr address = 0xcc; sfr page = 0 sfr definition 31.10. tmr2rll: ti mer 2 reload register low byte bit76543210 name tmr2rll[7:0] type r/w reset 00000000 bit name function 7:0 tmr2rll[7:0] timer 2 reload register low byte. tmr2rll holds the low byte of the reload value for timer 2. sfr definition 31.11. tmr2rlh: ti mer 2 reload register high byte bit76543210 name tmr2rlh[7:0] type r/w reset 00000000 bit name function 7:0 tmr2rlh[7:0] timer 2 reload register high byte. tmr2rlh holds the high byte of the reload value for timer 2. sfr definition 31.12. tmr2l: timer 2 low byte bit76543210 name tmr2l[7:0] type r/w reset 00000000 bit name function 7:0 tmr2l[7:0] timer 2 low byte. in 16-bit mode, the tmr2l register contains the low byte of the 16-bit timer 2. in 8-bit mode, tmr2l contains the 8-bit low byte timer value. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 256 preliminary rev. 0.71 sfr address = 0xcd; sfr page = 0 sfr definition 31.13. tmr2h timer 2 high byte bit76543210 name tmr2h[7:0] type r/w reset 00000000 bit name function 7:0 tmr2h[7:0] timer 2 low byte. in 16-bit mode, the tmr2h register contai ns the high byte of the 16-bit timer 2. in 8-bit mode, tmr2h contains the 8-bit high byte timer value. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 257 c8051f39x/37x 31.3. timer 3 timer 3 is a 16-bit timer formed by two 8-bit sfrs: tmr3l (low byte) and tmr3h (high byte). timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t3split bit (tmr3cn.3) defines the timer 3 operation mode. timer 3 may be clocked by the system clock, the syste m clock divided by 12, the external oscillator source divided by 8, or the internal low-fr equency oscillator divided by 8. the ex ternal clock mode is ideal for real- time clock (rtc) functionality, wher e the internal high-frequency oscilla tor drives the system clock while timer 3 is clocked by an external oscillator source. note that the external oscillato r source divided by 8 and the lfo source divided by 8 are synchronized with th e system clock when in all operating modes except suspend. when the internal oscillator is placed in suspend mode, the external clock/8 signal or the lfo/8 output can directly drive the timer. this allows the use of an exter nal clock or the lfo to wake up the device from suspend mode. the time r will continue to run in suspend mo de and count up. when the timer overflow occurs, the device will wake from suspen d mode, and begin executing code again. the timer value may be set prior to entering suspend, to overflow in the desired amount of time (number of clocks) to wake the device. if a wake-up source other than t he timer wakes the device from suspend mode, it may take up to three timer clocks before the timer regist ers can be read or written. during this time, the stsync bit in register oscicn will be set to 1, to indicate that it is not safe to read or write the timer reg- isters. important note: in internal lfo/8 mode, the divider for the internal lfo must be set to 1 for proper functionality. the timer will not operate if the lfo divider is not set to 1. 31.3.1. 16-bit time r with auto-reload when t3split (tmr3cn.3) is zero, timer 3 operates as a 16-bit timer with auto-reload. timer 3 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 3 reload registers (tmr3rlh and tmr3rll) is loaded in to the timer 3 register as shown in figure 31.7, and the timer 3 high byte overflow fl ag (tmr3cn.7) is set. if timer 3 interrupts are enabled (if eie1.7 is set), an interrupt will be generat ed on each timer 3 overflow. addition ally, if timer 3 in terrupts are enabled and the tf3len bit is set (tmr3cn. 5), an interr upt will be generated each time the lower 8 bits (tmr3l) overflow from 0xff to 0x00. figure 31.7. timer 3 16-bit mode block diagram sysclk tmr3l tmr3h tmr3rll tmr3rlh reload tclk 0 1 tr3 tmr3cn t3split t3xclk1 tf3cen tf3l tf3h t3xclk0 tr3 interrupt tf3len to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m external clock / 8 sysclk / 12 00 t3xclk[1:0] 01 11 internal lfo / 8 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 258 preliminary rev. 0.71 31.3.2. 8-bit timers with auto-reload when t3split is set, timer 3 operates as two 8-bi t timers (tmr3h and tmr3l). both 8-bit timers oper- ate in auto-reload mode as shown in figure 31.8. tmr3rll holds the reload value for tmr3l; tmr3rlh holds the reload value for tmr3h. the tr3 bit in tmr3cn handles the run control for tmr3h. tmr3l is always running when configured for 8-bit mode. each 8-bit timer may be configured to use sysclk, sysc lk divided by 12, the external oscillator clock source divided by 8, or the intern al low-frequency oscilla tor. the timer 3 clock select bits (t3mh and t3ml in ckcon) select either sy sclk or the clock defined by the timer 3 external clock select bits (t3xclk[1:0] in tmr3cn), as follows: the tf3h bit is set when tmr3h overflows from 0xff to 0x00; the tf3l bit is set when tmr3l overflows from 0xff to 0x00. when timer 3 interrupts are enabled, an interrupt is generated each time tmr3h over- flows. if timer 3 interrupts are enabled and tf3len (tmr3cn.5) is set, an interrupt is generated each time either tmr3l or tmr3h overflows. when tf3le n is enabled, software must check the tf3h and tf3l flags to determine the source of the timer 3 interrupt. the tf3h and tf3l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 31.8. timer 3 8-bit mode block diagram t3mh t3xclk[1:0] tmr3h clock source t3ml t3xclk[1:0] tmr3l clock source 0 00 sysclk / 12 0 00 sysclk / 12 0 01 external clock / 8 0 01 external clock / 8 0 10 reserved 0 10 reserved 0 11 internal lfo 0 11 internal lfo 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr3 1 0 tmr3h tmr3rlh reload reload tclk tmr3l tmr3rll interrupt tmr3cn t3split t3xclk1 tf3cen tf3len tf3l tf3h t3xclk0 tr3 to adc external clock / 8 sysclk / 12 00 t3xclk[1:0] 01 11 internal lfo / 8 ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 259 c8051f39x/37x 31.3.3. low-frequency oscillator (lfo) capture mode the low-frequency oscillator captur e mode allows the lfo clock to be measured against the system clock or an external oscillator so urce. timer 3 can be clocked from t he system clock, the system clock divided by 12, or the external oscillator divide d by 8, depending on th e t3ml (ckcon.6), and t3xclk[1:0] settings. setting tf3cen to 1 enables the lfo capture mode for timer 3. in this mode, t3split should be set to 0, as the full 16-bit timer is used. upon a falling e dge of the low-frequency o scillator, the contents of timer 3 (tmr3h:tmr3l) are loaded into the time r 3 reload registers (tmr3rlh:tmr3rll) and the tf3h flag is set. by recording the difference betw een two successive timer capture values, the lfo clock frequency can be determined with respect to the time r 3 clock. the timer 3 clock should be much faster than the lfo to achieve an accurate reading. this means that the lfo/8 should not be selected as the timer clock source in this mode. figure 31.9. timer 3 low-frequency oscillation capture mode block diagram external clock / 8 sysclk / 12 sysclk 0 1 00 01 t3xclk[1:0] ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr3l tmr3h tclk tr3 tmr3rll tmr3rlh capture low-frequency oscillator tmr3cn t3split t3xclk1 tf3cen tf3l tf3h t3xclk0 tr3 tf3len tf3cen interrupt www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 260 preliminary rev. 0.71 sfr address = 0x91; sfr page = 0 sfr definition 31.14. tm r3cn: timer 3 control bit76543210 name tf3h tf3l tf3len tf3cen t3split tr3 t3xclk[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 tf3h timer 3 high byte overflow flag. set by hardware when the timer 3 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 3 overfl ows from 0xffff to 0x0000. when the timer 3 interrupt is enabled, setting this bit causes the cpu to vector to the timer 3 interrupt service routine. this bit is not automatically cleared by hardware. 6 tf3l timer 3 low byte overflow flag. set by hardware when the timer 3 low byte overflows from 0xff to 0x00. tf3l will be set when the low byte overflows regardless of the timer 3 mode. this bit is not automatically cleared by hardware. 5tf3len timer 3 low byte interrupt enable. when set to 1, this bit enables timer 3 low byte interrupts. if timer 3 interrupts are also enabled, an interrupt will be generated when the low byte of timer 3 overflows. 4tf3cen timer 3 low-frequency oscillator capture enable. when set to 1, this bit enables timer 3 low-frequency oscilla tor capture mode. if tf3cen is set and timer 3 interrupts are enabled, an interrup t will be generated on a falling edge of the low-frequ ency oscillator output, and the current 16-bit timer value in tmr3h:tmr3l will be copied to tmr3rlh:tmr3rll. 3t3split timer 3 split mode enable. when this bit is set, timer 3 operates as two 8-bit timers with auto-reload. 0: timer 3 operates in 16-bit auto-reload mode. 1: timer 3 operates as two 8-bit auto-reload timers. 2tr3 timer 3 run control. timer 3 is enabled by setting this bit to 1. in 8-bit mode, this bit enables/disables tmr3h only; tmr3l is always enabled in split mode. 1:0 t3xclk[1:0] timer 3 external clock select. this bit selects the ?external? clock source for timer 3. if timer 3 is in 8-bit mode, this bit selects the external oscillator cloc k source for both ti mer bytes. however, the timer 3 clock select bits (t3mh and t3ml in register ckcon) may still be used to select between t he external clock and the syst em clock for either timer. 00: system clock divided by 12. 01: external clock divided by 8 (synchronized wi th sysclk when not in suspend). 10: reserved. 11: internal lfo/8 (synchronized with sysclk when not in suspend). www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 261 c8051f39x/37x sfr address = 0x92; sfr page = 0 sfr address = 0x93; sfr page = 0 sfr address = 0x94; sfr page = 0 sfr definition 31.15. tmr3rll: ti mer 3 reload register low byte bit76543210 name tmr3rll[7:0] type r/w reset 00000000 bit name function 7:0 tmr3rll[7:0] timer 3 reload register low byte. tmr3rll holds the low byte of the reload value for timer 3. sfr definition 31.16. tmr3rlh: ti mer 3 reload register high byte bit76543210 name tmr3rlh[7:0] type r/w reset 00000000 bit name function 7:0 tmr3rlh[7:0] timer 3 reload register high byte. tmr3rlh holds the high byte of the reload value for timer 3. sfr definition 31.17. tmr3l: timer 3 low byte bit76543210 name tmr3l[7:0] type r/w reset 00000000 bit name function 7:0 tmr3l[7:0] timer 3 low byte. in 16-bit mode, the tmr3l register contains the low byte of the 16-bit timer 3. in 8-bit mode, tmr3l contains the 8-bit low byte timer value. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 262 preliminary rev. 0.71 sfr address = 0x95; sfr page = 0 sfr definition 31.18. tmr3h timer 3 high byte bit76543210 name tmr3h[7:0] type r/w reset 00000000 bit name function 7:0 tmr3h[7:0] timer 3 high byte. in 16-bit mode, the tmr3h register co ntains the high byte of the 16-bit timer 3. in 8-bit mode, tmr3h contains the 8-bit high byte timer value. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 263 c8051f39x/37x 31.4. timer 4 timer 4 is a 16-bit timer formed by two 8-bit sfrs: tmr4l (low byte) and tmr4h (high byte). timer 4 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t4split bit (tmr4cn.3) defines timer 4 may be clocked by the system clock, the syst em clock divided by 12, or the external oscillator source divided by 8. note that th e external oscillator source divid ed by 8 is synchronized with the system clock. 31.4.1. 16-bit time r with auto-reload when t4split (tmr4cn.3) is zero, timer 4 operates as a 16-bit timer with auto-reload. timer 4 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 4 reload registers (tmr4rlh and tmr4rll) is loaded in to the timer 4 register as shown in figure 31.10, and the timer 4 high byte overflow fl ag (tmr4cn.7) is set. if timer 4 interrupts are enabled (if eie1.7 is set), an interrupt will be generat ed on each timer 4 overflow. addition ally, if timer 4 in terrupts are enabled and the tf4len bit is set (tmr4cn. 5), an interr upt will be generated each time the lower 8 bits (tmr4l) overflow from 0xff to 0x00. figure 31.10. timer 4 16-bit mode block diagram external clock / 8 sysclk / 12 sysclk tmr4l tmr4h tmr4rll tmr4rlh reload tclk 0 1 tr4 tmr4cn t4split t4css t4ce tf4l tf4h t4xclk tr4 0 1 t4xclk interrupt tf4len to adc ckcon1 t 4 m l t 4 m h t 5 m l t 5 m h www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 264 preliminary rev. 0.71 31.4.2. 8-bit timers with auto-reload when t4split is 1 and t4ce = 0, timer 4 operates as two 8-bit timers (tmr4h and tmr4l). both 8-bit timers operate in auto-reload mode as shown in figure 31.11. tmr4rll holds the reload value for tmr4l; tmr4rlh holds the reload value for tmr4h. the tr4 bit in tmr4cn handles the run control for tmr4h. tmr4l is always running when configured for 8-bit mode. each 8-bit timer may be c onfigured to use sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 4 clock select bits (t4mh and t4ml in ckcon1) select either sysclk or the clock defined by the timer 4 external cloc k select bit (t4xclk in tmr4cn), as follows: the tf4h bit is set when tmr4h overflows from 0xff to 0x00; the tf4l bit is set when tmr4l overflows from 0xff to 0x00. when timer 4 interrupts are enabled, an interrupt is generated each time tmr4h over- flows. if timer 4 interrupts are enabled and tf4len (tmr4cn.5) is set, an interrupt is generated each time either tmr4l or tmr4h overflows. when tf4le n is enabled, software must check the tf4h and tf4l flags to determine the source of the timer 4 interrupt. the tf4h and tf4l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 31.11. timer 4 8-bit mode block diagram t4mh t4xclk tmr4h clock source t4ml t4xclk tmr4l clock source 0 0 sysclk/12 0 0 sysclk/12 0 1 external clock/8 0 1 external clock/8 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr4 external clock / 8 sysclk / 12 0 1 t4xclk 1 0 tmr4h tmr4rlh reload reload tclk tmr4l tmr4rll interrupt tmr4cn t4split t4css t4ce tf4len tf4l tf4h t4xclk tr4 to adc ckcon1 t 4 m l t 4 m h t 5 m l t 5 m h www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 265 c8051f39x/37x sfr address = 0x91; sfr page = f sfr definition 31.19. tm r4cn: timer 4 control bit76543210 name tf4h tf4l tf4len t4split tr4 t4xclk type r/w r/w r/w r r/w r/w r r/w reset 00000000 bit name function 7tf4h timer 4 high byte overflow flag. set by hardware when the timer 4 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occu r when timer 4 overflows from 0xffff to 0x0000. when the timer 4 interrupt is enabled, setting this bit causes the cpu to vector to the timer 4 interrupt service routine. this bit is not automatically cleared by hardware. 6tf4l timer 4 low byte overflow flag. set by hardware when the timer 4 low byte overflows from 0xff to 0x00. tf4l will be set when the low byte ov erflows regardless of the timer 4 mode. this bit is not automat ically cleared by hardware. 5 tf4len timer 4 low byte interrupt enable. when set to 1, this bit enables time r 4 low byte interrupts. if timer 4 interrupts are also enab led, an interrupt will be generated when the low byte of timer 4 overflows. 4 unused read = 0b; write = don?t care. 3 t4split timer 4 split mode enable. when this bit is set, timer 4 oper ates as two 8-bit timers with auto- reload. 0: timer 4 operates in 16-bit auto-reload mode. 1: timer 4 operates as two 8-bit auto-reload timers. 2tr4 timer 4 run control. timer 4 is enabled by setting this bit to 1. in 8-bit mode, this bit enables/ disables tmr4h only; tmr4l is always enabled in split mode. 1 unused read = 0b; write = don?t care. 0t4xclk timer 4 external clock select. this bit selects the external clo ck source for timer 4. however, the timer 4 clock select bits (t4mh an d t4ml in register ckcon1) may still be used to select between the ex ternal clock and the system clock for either timer. 0: timer 4 clock is the system clock divided by 12. 1: timer 4 clock is the external clock divided by 8 (synchronized with sysclk). www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 266 preliminary rev. 0.71 sfr address = 0x92; sfr page = f sfr address = 0x93; sfr page = f sfr address = 0x94; sfr page = f sfr definition 31.20. tmr4rll: ti mer 4 reload register low byte bit76543210 name tmr4rll[7:0] type r/w reset 00000000 bit name function 7:0 tmr4rll[7:0] timer 4 reload register low byte. tmr4rll holds the low byte of the reload value for timer 4. sfr definition 31.21. tmr4rlh: ti mer 4 reload register high byte bit76543210 name tmr4rlh[7:0] type r/w reset 00000000 bit name function 7:0 tmr4rlh[7:0] timer 4 reload register high byte. tmr4rlh holds the high byte of the reload value for timer 4. sfr definition 31.22. tmr4l: timer 4 low byte bit76543210 name tmr4l[7:0] type r/w reset 00000000 bit name function 7:0 tmr4l[7:0] timer 4 low byte. in 16-bit mode, the tmr4l register contains the low byte of the 16-bit timer 4. in 8-bit mode, tmr4l contains the 8-bit low byte timer value. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 267 c8051f39x/37x sfr address = 0x95; sfr page = f sfr definition 31.23. tmr4h timer 4 high byte bit76543210 name tmr4h[7:0] type r/w reset 00000000 bit name function 7:0 tmr4h[7:0] timer 4 high byte. in 16-bit mode, the tmr4h register contains the high byte of the 16-bit timer 4. in 8-bit mode, tmr4h contains the 8-bit high byte timer value. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 268 preliminary rev. 0.71 31.5. timer 5 timer 5 is a 16-bit timer formed by two 8-bit sfrs: tmr5l (low byte) and tmr5h (high byte). timer 5 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t5split bit (tmr5cn.3) defines timer 5 may be clocked by the system clock, the syst em clock divided by 12, or the external oscillator source divided by 8. note that th e external oscillator source divid ed by 8 is synchronized with the system clock. 31.5.1. 16-bit time r with auto-reload when t5split (tmr5cn.3) is zero, timer 5 operates as a 16-bit timer with auto-reload. timer 5 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 5 reload registers (tmr5rlh and tmr5rll) is loaded in to the timer 5 register as shown in figure 31.12, and the timer 5 high byte overflow fl ag (tmr5cn.7) is set. if timer 5 interrupts are enabled (if eie1.7 is set), an interrupt will be generat ed on each timer 5 overflow. addition ally, if timer 5 in terrupts are enabled and the tf5len bit is set (tmr5cn. 5), an interr upt will be generated each time the lower 8 bits (tmr5l) overflow from 0xff to 0x00. figure 31.12. timer 5 16-bit mode block diagram external clock / 8 sysclk / 12 sysclk tmr5l tmr5h tmr5rll tmr5rlh reload tclk 0 1 tr5 tmr5cn t5split t5css t5ce tf5l tf5h t5xclk tr5 0 1 t5xclk interrupt tf5len to adc ckcon1 t 4 m l t 4 m h t 5 m l t 5 m h www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 269 c8051f39x/37x 31.5.2. 8-bit timers with auto-reload when t5split is 1 and t5ce = 0, timer 5 operates as two 8-bit timers (tmr5h and tmr5l). both 8-bit timers operate in auto-reload mode as shown in figure 31.13. tmr5rll holds the reload value for tmr5l; tmr5rlh holds the reload value for tmr5h. the tr5 bit in tmr5cn handles the run control for tmr5h. tmr5l is always running when configured for 8-bit mode. each 8-bit timer may be c onfigured to use sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 5 clock select bits (t5mh and t5ml in ckcon1) select either sysclk or the clock defined by the timer 5 external cloc k select bit (t5xclk in tmr5cn), as follows: the tf5h bit is set when tmr5h overflows from 0xff to 0x00; the tf5l bit is set when tmr5l overflows from 0xff to 0x00. when timer 5 interrupts are enabled, an interrupt is generated each time tmr5h over- flows. if timer 5 interrupts are enabled and tf5len (tmr5cn.5) is set, an interrupt is generated each time either tmr5l or tmr5h overflows. when tf5le n is enabled, software must check the tf5h and tf5l flags to determine the source of the timer 5 interrupt. the tf5h and tf5l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 31.13. timer 5 8-bit mode block diagram t5mh t5xclk tmr5h clock source t5ml t5xclk tmr5l clock source 0 0 sysclk/12 0 0 sysclk/12 0 1 external clock/8 0 1 external clock/8 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr5 external clock / 8 sysclk / 12 0 1 t5xclk 1 0 tmr5h tmr5rlh reload reload tclk tmr5l tmr5rll interrupt tmr5cn t5split t5css t5ce tf5len tf5l tf5h t5xclk tr5 to adc ckcon1 t 4 m l t 4 m h t 5 m l t 5 m h www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 270 preliminary rev. 0.71 sfr address = 0xc8; sfr page = f; bit-addressable sfr definition 31.24. tm r5cn: timer 5 control bit76543210 name tf5h tf5l tf5len t5split tr5 t5xclk type r/w r/w r/w r r/w r/w r r/w reset 00000000 bit name function 7 tf5h timer 5 high byte overflow flag. set by hardware when the timer 5 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 5 overflows from 0xffff to 0x0000. when the timer 5 interrupt is enabled, setting this bit causes the cpu to vector to the timer 5 interrupt service routine. this bit is not auto- matically cleared by hardware. 6 tf5l timer 5 low byte overflow flag. set by hardware when the timer 5 low byte overflows from 0xff to 0x00. tf5l will be set when the low byte over flows regardless of the timer 5 mode. this bit is not automa tically cleared by hardware. 5 tf5len timer 5 low byte interrupt enable. when set to 1, this bit enables time r 5 low byte interrupts. if timer 5 interrupts are also enabled, an in terrupt will be gener ated when the low byte of timer 5 overflows. 4 unused read = 0b; write = don?t care. 3 t5split timer 5 split mode enable. when this bit is set, timer 5 operates as two 8-bit timers with auto-reload. 0: timer 5 operates in 16-bit auto-reload mode. 1: timer 5 operates as two 8-bit auto-reload timers. 2tr5 timer 5 run control. timer 5 is enabled by setting this bit to 1. in 8-bit mode, this bit enables/ disables tmr5h only; tmr5l is always enabled in split mode. 1 unused read = 0b; write = don?t care. 0t5xclk timer 5 external clock select. this bit selects the external clock so urce for timer 5. however, the timer 5 clock select bits (t5mh and t5ml in register ckcon1) may still be used to select between the external clock and the system clock for either timer. 0: timer 5 clock is the system clock divided by 12. 1: timer 5 clock is the external clock divided by 8 (synchronized with sys- clk). www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 271 c8051f39x/37x sfr address = 0xca; sfr page = f sfr address = 0xcb; sfr page = f sfr address = 0xcc; sfr page = f sfr definition 31.25. tmr5rll: ti mer 5 reload register low byte bit76543210 name tmr5rll[7:0] type r/w reset 00000000 bit name function 7:0 tmr5rll[7:0] timer 5 reload register low byte. tmr5rll holds the low byte of the reload value for timer 5. sfr definition 31.26. tmr5rlh: ti mer 5 reload register high byte bit76543210 name tmr5rlh[7:0] type r/w reset 00000000 bit name function 7:0 tmr5rlh[7:0] timer 5 reload register high byte. tmr5rlh holds the high byte of the reload value for timer 5. sfr definition 31.27. tmr5l: timer 5 low byte bit76543210 name tmr5l[7:0] type r/w reset 00000000 bit name function 7:0 tmr5l[7:0] timer 5 low byte. in 16-bit mode, the tmr5l register co ntains the low byte of the 16-bit timer 5. in 8-bit mode, tmr5l contains the 8-bit low byte timer value. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 272 preliminary rev. 0.71 sfr address = 0xcd; sfr page = f sfr definition 31.28. tmr5h timer 5 high byte bit76543210 name tmr5h[7:0] type r/w reset 00000000 bit name function 7:0 tmr5h[7:0] timer 5 high byte. in 16-bit mode, the tmr5h register contains the high byte of the 16- bit timer 5. in 8-bit mode, tmr5h contains the 8-bit high byte timer value. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 273 c8051f39x/37x 32. programmable counter array the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu intervention than the standard 8051 counter/timers. th e pca consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. each capt ure/compare module has its own associated i/o line (cexn) which is routed through the crossbar to port i/o when enabled. the counter/timer is driven by a programmable timebase that can select between seve n sources: system clock, system clock divided by four, system clock divided by twelve, the external o scillator clock source divide d by 8, low frequency oscil- lator divided by 8, timer 0 overflows, or an external clock signal on the eci i nput pin. each capture/com- pare module may be configured to operate independently in one of six modes: edge-triggered capture, software timer, high-speed output, frequency output, 8 to 11-bit pwm, or 16-bit pwm (each mode is described in section ?32. 3. capture/compare modules? on page 276). the exter nal oscillator clock option is ideal for real-time clock (rtc) functionality, allowing the pca to be clocked by a precision external oscil- lator while the internal oscillator dr ives the system clock. the pca is configured and cont rolled through the system controller's special function registers. the pca block diagram is shown in figure 32.1 important note: the pca module 2 may be used as a watchdog timer (wdt), and is enabled in this mode following a system reset. access to certain pca registers is restricted while wdt mode is enabled . see section 32.4 for details. figure 32.1. pca block diagram capture/compare module 1 capture/compare module 0 capture/compare module 2 / wdt cex1 eci crossbar cex2 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 lfo/8 www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 274 preliminary rev. 0.71 32.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bi t sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/timer and pca0l is the low byte (lsb). reading pc a0l automatically latches the value of pca0h into a ?snapshot? register; the following pca0h read accesses this ?snapshot? register. reading the pca0l register first guarantees an accu rate reading of the entire 16-bit pca0 counter. reading pca0h or pca0l does not disturb the counter operation. the cps2 ? cps0 bits in the pca0md register select the timebase for the counter/timer as shown in table 32.1. when the counter/timer overflows from 0xffff to 0x0 000, the counter overflow flag (cf) in pca0md is set to logic 1 and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an interrupt request. the cf bit is not automatically cleared by hardware when the cpu vectors to the inte rrupt service routine, and must be cleared by soft- ware. clearing the cidl bit in the pca0md register a llows the pca to continue normal operation while the cpu is in idle mode. figure 32.2. pca counter/timer block diagram table 32.1. pca timebase input options cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 011 high-to-low transitions on eci (max rate = system clock divided by 4) 1 0 0 system clock 1 0 1 external oscillator source divided by 8 * 1 1 0 low frequency oscillator divided by 8 * 111reserved note: synchronized with the system clock. pca0cn c f c r c c f 0 c c f 2 c c f 1 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 idle 0 1 pca0h pca0l snapshot register to sfr bus overflow to pca interrupt system cf pca0l read to pca modules sysclk/12 sysclk/4 timer 0 overflow eci 000 001 010 011 100 101 sysclk external clock/8 lfo/8 110 www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 275 c8051f39x/37x 32.2. pca0 interrupt sources figure 32.3 shows a diagram of the pca interrupt tree . there are five independent event flags that can be used to generate a pca0 interrupt. they are: the main pca counter overflow flag (cf), which is set upon a 16-bit overflow of the pca0 counter, an intermediat e overflow flag (covf), which can be set on an over- flow from the 8th, 9th, 10th, or 11th bit of the pca0 counter, and the individual flags for each pca channel (ccf0, ccf1, and ccf2), which are set according to the operation mode of that module. these event flags are always set when the trigger condition occurs. each of these flags can be individually selected to generate a pca0 interrupt, using the corresponding interrupt enable flag (ecf for cf, ecov for covf, and eccfn for each ccfn). pca0 interrupts must be globally enabled before any individual interrupt sources are recognized by the processor. pca0 interr upts are globally enabled by setting the ea bit and the epca0 bit to logic 1. figure 32.3. pca interrupt block diagram pca0cn c f c r c c f 0 c c f 2 c c f 1 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 0 1 pca module 0 (ccf0) pca module 1 (ccf1) eccf1 0 1 eccf0 0 1 pca module 2 (ccf2) eccf2 pca counter/timer 16- bit overflow 0 1 interrupt priority decoder epca0 0 1 ea 0 1 pca0cpmn (for n = 0 to 2) p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca counter/timer 8, 9, 10 or 11-bit overflow 0 1 set 8, 9, 10, or 11 bit operation pca0pwm a r s e l e c o v c l s e l 0 c l s e l 1 c o v f www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 276 preliminary rev. 0.71 32.3. capture/compare modules each module can be configured to operate independ ently in one of six operat ion modes: edge-triggered capture, software timer, high-speed output, frequency output, 8 to 11-bit pulse width modulator, or 16-bit pulse width modulator. each module has special functi on registers (sfrs) associ ated with it in the cip- 51 system controller. these registers are used to exchange data with a module and configure the module's mode of operation. table 32.2 summarizes the bit settings in the pca0cpmn and pca0pwm registers used to select the pca capture/compare module?s operating mode. note that all modules set to use 8, 9, 10, or 11-bit pwm mode must use the same cycle length (8?11 bits). setting the eccfn bit in a pca0cpmn register enables the module's ccfn interrupt. table 32.2. pca0cpm and pca0pwm bit settings for pca capture/compare modules operational mode pca0cpmn pca0pwm bit number76543210765 4?2 1?0 capture triggered by positive edge on cexn xx10000a0xbxxx xx capture triggered by negative edge on cexn xx01000a0xbxxx xx capture triggered by any transition on cexn xx11000a0xbxxx xx software timer xc00100a0xbxxx xx high speed output xc00110a0xbxxx xx frequency output xc00011a0xbxxx xx 8-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a 0 x b xxx 00 9-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a d x b xxx 01 10-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a d x b xxx 10 11-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a d x b xxx 11 16-bit pulse width modulator 1 c 0 0 e 0 1 a 0 x b xxx xx notes: 1. x = don?t care (no functional difference for individual module if 1 or 0). 2. a = enable interrupts for this module (pca interrupt triggered on ccfn set to 1). 3. b = enable 8th, 9th, 10th or 11th bit overflow interrupt (depends on setting of clsel[1:0]). 4. c = when set to 0, the digital comparator is off. for high speed and frequency output modes, the associated pin will not toggle. in any of the pwm modes, this generates a 0% duty cycle (output = 0). 5. d = selects whether the capture/compare register (0) or the auto-reload register (1) for the associated channel is accessed via addresses pca0cphn and pca0cpln. 6. e = when set, a match event will cause the ccfn flag for the associated channel to be set. 7. all modules set to 8, 9, 10 or 11-bit pw m mode use the same cycle length setting. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 277 c8051f39x/37x 32.3.1. edge-triggered capture mode in this mode, a valid transition on the cexn pin ca uses the pca to capture th e value of the pca counter/ timer and load it into the corresponding module's 16-bit capture/compare register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cpmn register are used to select the type of transi- tion that triggers the capture: low-to-high transition (p ositive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an inte rrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt ser- vice routine, and must be cleared by software. if both cappn and capn n bits are set to logic 1, then the state of the port pin associated wit h cexn can be read directly to de termine whether a rising-edge or fall- ing-edge caused the capture. figure 32.4. pca capture mode diagram note: the cexn input sign al must remain high or lo w for at least 2 system clock cycles to be recognized by the hardware. pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn 0 1 0 1 (to ccfn) pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt x 000x x www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 278 preliminary rev. 0.71 32.3.2. software timer (compare) mode in software timer mode, the pca c ounter/timer value is compared to the module's 16-bit capture/compare register (pca0cphn and pca0cpln). when a matc h occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interr upt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt ser- vice routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn regis- ter enables software timer mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. figure 32.5. pca software timer mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 00 00 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 279 c8051f39x/37x 32.3.3. high-speed output mode in high-speed output mode, a module?s associated cexn pin is toggled each time a match occurs between the pca counter and the module's 16- bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compar e flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not auto- matically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by software. setting the togn, matn, and ecomn bi ts in the pca0cpmn register enables the high- speed output mode. if ecomn is cleare d, the associated pin will retain it s state, and not toggle on the next match event. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. figure 32.6. pca high-speed output mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 0 1 00 0x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x cexn crossbar port i/o toggle 0 1 togn pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 280 preliminary rev. 0.71 32.3.4. frequency output mode frequency output mode produces a programmable-freq uency square wave on the module?s associated cexn pin. the capture/compare module high byte holds the number of pca clocks to count before the out- put is toggled. the frequency of the square wave is then defined by equation 32.1. equation 32.1. square wave frequency output where f pca is the frequency of the clock selected by the cps2 ? 0 bits in the pca mode register, pca0md. the lower byte of the capture/compare modu le is compared to the pca counter low byte; on a match, n is toggled and the offset held in the high byte is added to the matched value in pca0cpln. fre- quency output mode is enabled by setting the ecom n, togn, and pwmn bits in the pca0cpmn register. note that the matn bit should normally be set to 0 in this mode. if the matn bit is set to 1, the ccfn flag for the channel will be set when the 16-bit pca0 counte r and the 16-bit capture/ compare register for the channel are equal. figure 32.7. pca frequency output mode 32.3.5. 8-bit, 9-bit, 10-bit and 11-bit pulse width modulator modes each module can be used independently to generate a pulse width modulated (pwm) output on its associ- ated cexn pin. the frequency of the output is depe ndent on the timebase for the pca counter/timer, and the setting of the pwm cycle length (8, 9, 10 or 11 -bits). for backwards-compa tibility with the 8-bit pwm mode available on other devices, the 8-bit pwm mode operates slightly different than 9, 10 and 11-bit pwm modes. it is important to note that all channels configured for 8/9/10/11-bit pwm mode will use the same cycle length. it is not possible to configure one channel for 8-bit pwm mode and another for 11- bit mode (for example). however, other pca channels can be configured to pin capture, high-speed out- put, software timer, frequency output, or 16-bit pwm mode independently. f cexn f pca 2 pca 0 cphn ? ------------------- --------------------- - = note: a value of 0x00 in the pca0cphn re gister is equal to 256 for this equation. 8-bit comparator pca0l enable pca timebase match pca0cphn 8-bit adder pca0cpln adder enable cexn crossbar port i/o toggle 0 1 togn 000 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x enb enb 0 1 write to pca0cpln write to pca0cphn reset www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 281 c8051f39x/37x 32.3.5.1. 8-bit pulse width modulator mode the duty cycle of the pwm output signal in 8-bit pwm mode is varied using the module's pca0cpln cap- ture/compare register. when the value in the low byte of the pca counter/timer (pca0l) is equal to the value in pca0cpln, the output on th e cexn pin will be set. when the coun t value in pca0l overflows, the cexn output will be reset (see figu re 32.8). also, when th e counter/timer low byte (pca0l) overflows from 0xff to 0x00, pca0cpln is reloaded automatically with the value stored in the module?s capture/compare high byte (pca0cphn) without software intervention. setting the ecomn and pwmn bits in the pca0cpmn register, and setting the clsel bits in register pca0pwm to 00b enables 8-bit pulse width modulator mode. if the matn bit is se t to 1, the ccfn flag for the modu le will be set each time an 8-bit comparator match (rising edge) occurs. the covf flag in pca0pwm can be used to detect the overflow (falling edge), which will occur every 256 pca clock cyc les. the duty cycle for 8-bit pwm mode is given in equation 32.2. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 32.2. 8-bit pwm duty cycle using equation 32.2, the largest duty cycle is 10 0% (pca0cphn = 0), and the smallest duty cycle is 0.39% (pca0cphn = 0xff). a 0% duty cycle may be generated by clearing the ecomn bit to 0. figure 32.8. pca 8-bit pwm mode diagram duty cycle 256 pca 0 cphn ? ?? 256 ------------------ ----------------- ---------------- = 8-bit comparator pca0l pca0cpln pca0cphn cexn crossbar port i/o enable overflow pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 pca0pwm a r s e l e c o v c l s e l 0 c l s e l 1 c o v f x0 0 0 enb enb 0 1 write to pca0cpln write to pca0cphn reset covf www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 282 preliminary rev. 0.71 32.3.5.2. 9/10/11-bit pulse width modulator mode the duty cycle of the pwm output signa l in 9/10/11-bit pwm mode should be varied by writing to an ?auto- reload? register, which is dual-mapped into the pc a0cphn and pca0cpln register locations. the data written to define the duty cycle should be right-just ified in the registers. the auto-reload registers are accessed (read or written) when the bit arsel in pca0pwm is set to 1. the capture/compare registers are accessed when arsel is set to 0. when the least-significant n bits of the pca0 counter match the value in the associated module?s capture/ compare register (pca0cpn), the output on cexn is asserted high. when the counter overflows from the nth bit, cexn is asserted low (see figure 32.9). upon an overflow from the nth bi t, the covf flag is set, and the value stored in the module?s auto-reload regi ster is loaded into the capture/compare register. the value of n is determined by the clsel bits in register pca0pwm. the 9, 10 or 11-bit pwm mode is selected by setting the ecomn and pwmn bits in the pca0cpmn regis- ter, and setting the clsel bits in register pca0pwm to the desired cycle length (other than 8-bits). if the matn bit is set to 1, the ccfn fl ag for the module will be set each ti me a comparator match (rising edge) occurs. the covf flag in pca0pwm can be used to detect the overflow (f alling edge), which will occur every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) pca clock cycles . the duty cycle for 9/10/11-bit pwm mode is given in equation 32.2, where n is the number of bits in the pwm cycle. important note about pca0cphn and pca0cpln registers : when writing a 16-bit value to the pca0cpn registers, the low byte should always be wr itten first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 32.3. 9, 10, and 11-bit pwm duty cycle a 0% duty cycle may be generated by clearing the ecomn bit to 0. figure 32.9. pca 9, 10 and 11-bit pwm mode diagram duty cycle 2 n pca 0 cpn ? ?? 2 n ------------------ -------------- ----------- - = n-bit comparator pca0h:l (capture/compare) pca0cph:ln (right-justified) (auto-reload) pca0cph:ln (right-justified) cexn crossbar port i/o enable overflow of n th bit pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 pca0pwm a r s e l e c o v c l s e l 0 c l s e l 1 c o v f x enb enb 0 1 write to pca0cpln write to pca0cphn reset r/w when arsel = 1 r/w when arsel = 0 set ?n? bits: 01 = 9 bits 10 = 10 bits 11 = 11 bits www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 283 c8051f39x/37x 32.3.6. 16-bit pulse width modulator mode a pca module may also be operated in 16-bit pwm mode. 16-bit pwm mode is independent of the other (8/9/10/11-bit) pwm modes. in this mode, the 16-bit capture/compare module defines the number of pca clocks for the low time of the pwm signal. when the pca counter matches the module contents, the out- put on cexn is asserted high; when the 16-bit counter overflows, cexn is asserted low. to output a vary- ing duty cycle, new value writes should be synchr onized with pca ccfn match interrupts. 16-bit pwm mode is enabled by setting the ecomn, pwmn, and pw m16n bits in the pca0cpmn register. for a vary- ing duty cycle, match interrupts should be enabled (eccfn = 1 and matn = 1) to help synchronize the capture/compar e register writes. if the matn bit is set to 1, the ccfn flag for the module will be set each time a 16-bit comparator match (rising edge) occurs. the cf flag in pca0cn can be used to detect the overflow (falling edge). the duty cycle for 16 -bit pwm mode is given by equation 32.4. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 32.4. 16-bit pwm duty cycle using equation 32.4, the largest duty cycle is 10 0% (pca0cpn = 0), and the smallest duty cycle is 0.0015% (pca0cpn = 0xffff). a 0% duty cycle may be generated by clearing the ecomn bit to 0. figure 32.10. pca 16-bit pwm mode duty cycle 65536 pca 0 cpn ? ?? 65536 ------------------ ------------------ ---------------- - = pca0cpln pca0cphn enable pca timebase 00x0 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 1 16-bit comparator cexn crossbar port i/o overflow q q set clr s r match pca0h pca0l enb enb 0 1 write to pca0cpln write to pca0cphn reset www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 284 preliminary rev. 0.71 32.4. watchdog timer mode a programmable watchdog timer (wdt) function is av ailable through the pca module 2. the wdt is used to generate a reset if the time between writes to th e wdt update register (pca0cph2) exceed a specified limit. the wdt can be configured and enabled/disabled as needed by software. with the wdte bit set in the pca0md register, modu le 2 operates as a watchdog timer (wdt). the mod- ule 2 high byte is compared to the pca counter high byte; the module 2 low byte holds the offset to be used when wdt updates are performed. the watchdog timer is enabled on reset. writes to some pca registers are restricted while the watchdog timer is enabled. the wdt will generate a reset shortly after code begins execution. to avoid this re set, the wdt should be explicitly disabled (and option- ally re-configured and re-enabled if it is used in the system). 32.4.1. watchdog timer operation while the wdt is enabled: ? pca counter is forced on. ? writes to pca0l and pca0h are not allowed. ? pca clock source bits (cps2 ? cps0) are frozen. ? pca idle control bit (cidl) is frozen. ? module 2 is forced into software timer mode. ? writes to the module 2 mode register (pca0cpm2) are disabled. while the wdt is enabled, writes to the cr bit will not change the pca counter state; the counter will run until the wdt is disabled. the pca counter run control bit (cr) will re ad zero if the wdt is enabled but user software has not enabled th e pca counter. if a match occurs between pca0cph2 and pca0h while the wdt is enabled, a reset will be generated. to pr event a wdt reset, the wd t may be up dated with a write of any value to pca0cph2. up on a pca0cph2 write, pca0h plus the offset held in pca0cpl2 is loaded into pca0cph2 (see figure 32.11). figure 32.11. pca module 2 with watchdog timer enabled pca0h enable pca0l overflow reset pca0cpl2 8-bit adder pca0cph2 adder enable pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 match write to pca0cph2 8-bit comparator www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 285 c8051f39x/37x the 8-bit offset held in pca0cph2 is compared to th e upper byte of the 16-bit pca counter. this offset value is the number of pca0l overflows before a re set. up to 256 pca clocks may pass before the first pca0l overflow occurs, depending on the value of th e pca0l when the update is performed. the total off- set is then given (in pca clocks) by equation 32.5, wher e pca0l is the value of the pca0l register at the time of the update. equation 32.5. watchdog timer offset in pca clocks the wdt reset is generated when pca0l overflow s while there is a match between pca0cph2 and pca0h. software may force a wdt reset by writing a 1 to the ccf2 flag (pca0cn.2) while the wdt is enabled. 32.4.2. watchdog timer usage to configure the wdt, perform the following tasks: 1. disable the wdt by writing a 0 to the wdte bit. 2. select the desired pca clock source (with the cps2 ? cps0 bits). 3. load pca0cpl2 with the desi red wdt update offset value. 4. configure the pca idle mode (set cidl if the wdt should be suspended while the cpu is in idle mode). 5. enable the wdt by setting the wdte bit to 1. 6. reset the wdt timer by writing to pca0cph2. the pca clock source and idle mode select cannot be changed while the wdt is enabled. the watchdog timer is enabled by setting the wdte or wdlck bits in the pca0md register. when wdlck is set, the wdt cannot be disabled until the next system reset. if wdlck is not se t, the wdt is disabled by clearing the wdte bit. the wdt is enabled following any rese t. the pca0 counter clock defaults to the system clock divided by 12, pca0l defaults to 0x00, and pca0cpl2 defaults to 0x00. using equation 32.5, this results in a wdt timeout interval of 256 pca clock cycles, or 3072 sys tem clock cycles. table 32.3 lists some example time- out intervals for typical system clocks. table 32.3. watchdog timer timeout intervals 1 system clock (hz) pca0cpl2 timeout interval (ms) 24,500,000 255 32.1 24,500,000 128 16.2 24,500,000 32 4.1 3,062,500 2 255 257 3,062,500 2 128 129.5 3,062,500 2 32 33.1 32,000 255 24576 32,000 128 12384 32,000 32 3168 notes: 1. assumes sysclk/12 as the pca clock source, and a pca0l value of 0x00 at the update time. 2. internal sysclk reset frequency = internal oscillator divided by 8. offset 256 pca 0 cpl 2 ? ?? 256 pca 0 l ? ?? + = www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 286 preliminary rev. 0.71 32.5. comparator clear function in 8/9/10/11/16-bit pwm modes, th e comparator clear function utilizes the comparator0 output synchro- nized to the system clock to clear cexn to logic low for the current pwm cycle. this comparator clear func- tion can be enabled for each pwm channel by setting the cpcen bits to 1 in the pca0clr sfr (see sfr definition 32.4). when the comparator clear function is disabled, cexn is unaffected. see figure 32.12. figure 32.12. comparator clear function diagram the asynchronous comparator0 output is logic high when the voltage of cp0+ is greater than cp0- and logic low when the voltage of cp0+ is less than cp0-. the polarity of the comparator0 output is used to clear cexn as follows: when cpcpol = 0, cexn is fo rced to logic low on the falling edge of the comparator0 output (see figure 32.13); when cpcpol = 0, cexn is forced logic low on the rising edge of the compartor0 output (see figure 32.14). figure 32.13. cexn with cpcen = 1, cpcpol = 0 cp0 + cp0 - comparator0 input mux pca0clr cpce0 cpce1 cpce2 cpcpol pca0cpmn eccfn pwmn togn matn capnn cappn ecomn pwm16n 0 1 clear cexn to logic low for current pwm cycle cexn (cpcen = 0) cexn (cpcen = 1) comparator0 output (cpcpol = 0) www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 287 c8051f39x/37x figure 32.14. cexn with cpcen = 1, cpcpol = 1 in the pwm cycle following the current cycle, shou ld the comparator0 output remain logic low when cpcpol = 0 or logic high when cpcpol = 1, cexn will continue to be logic lo w. see figure 32.15 and figure 32.16. figure 32.15. cexn with cpcen = 1, cpcpol = 0 figure 32.16. cexn with cpcen = 1, cpcpol = 1 cexn (cpcen = 0) cexn (cpcen = 1) comparator0 output (cpcpol = 1) cexn (cpcen = 0) cexn (cpcen = 1) comparator0 output (cpcpol = 0) cexn (cpcen = 0) cexn (cpcen = 1) comparator0 output (cpcpol = 1) www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 288 preliminary rev. 0.71 32.6. register d escriptions for pca0 following are detailed descriptions of the special func tion registers related to the operation of the pca. sfr address = 0xd8; sfr page = a ll pages; bit-addressable sfr definition 32.1. pca0cn: pca control bit76543210 name cf cr ccf2 ccf1 ccf0 type r/w r/w r r r r/w r/w r/w reset 00000000 bit name function 7cf pca counter/timer overflow flag. set by hardware when the pca counter/timer overflows from 0xffff to 0x0000. when the counter/timer overflow (cf) interrupt is enabled, setting this bit causes the cpu to vector to th e pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. 6cr pca counter/timer run control. this bit enables/disables the pca counter/timer. 0: pca counter/timer disabled. 1: pca counter/timer enabled. 5:3 unused unused. read = 000b, write = don't care. 2ccf2 pca module 2 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf2 interrupt is enabled, setting this bit caus es the cpu to vector to the pca inter- rupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. 1ccf1 pca module 1 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf1 interrupt is enabled, setting this bit caus es the cpu to vector to the pca inter- rupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. 0ccf0 pca module 0 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf0 interrupt is enabled, setting this bit caus es the cpu to vector to the pca inter- rupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 289 c8051f39x/37x sfr address = 0xd9; sfr page = all pages sfr definition 32.2. pca0md: pca mode bit76543210 name cidl wdte wdlck cps2 cps1 cps0 ecf type r/w r/w r/w r r/w r/w r/w r/w reset 01000000 bit name function 7cidl pca counter/timer idle control. specifies pca behavior when cpu is in idle mode. 0: pca continues to function normally wh ile the system controller is in idle mode. 1: pca operation is suspended while the system controller is in idle mode. 6wdte watchdog timer enable. if this bit is set, pca module 2 is used as the watchdog timer. 0: watchdog timer disabled. 1: pca module 2 enabled as watchdog timer. 5 wdlck watchdog timer lock. this bit locks/unlocks the watchdog ti mer enable. when wdlck is set, the watchdog timer may not be disabled until the next system reset. 0: watchdog timer enable unlocked. 1: watchdog timer enable locked. 4 unused unused. read = 0b, write = don't care. 3:1 cps[2:0] pca counter/timer pulse select. these bits select the timebase source for the pca counter 000: system clock divided by 12 001: system clock divided by 4 010: timer 0 overflow 011: high-to-low transitions on eci (max rate = system clock divided by 4) 100: system clock 101: external clock divided by 8 (synchronized with the system clock) 110: low frequency osc illator divided by 8 111: reserved 0ecf pca counter/timer overfl ow interrupt enable. this bit sets the masking of the pca co unter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca counter/timer overflow interrupt request when cf (pca0cn.7) is set. note: when the wdte bit is set to 1, the other bits in the pca0md register cannot be modified. to change the contents of the pca0md register, the watchdog timer must first be disabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 290 preliminary rev. 0.71 sfr address = 0xf7; sfr page = all pages sfr definition 32.3. pca0pwm : pca pwm configuration bit76543210 name arsel ecov covf clsel[1:0] type r/w r/w r/w r r r r/w reset 00000000 bit name function 7 arsel auto-reload register select. this bit selects whether to read and write the normal pca capture/com- pare registers (pca0cpn), or the auto-reload registers at the same sfr addresses. this function is used to define the reload value for 9, 10, and 11-bit pwm modes. in all other modes, the auto-reload regis- ters have no function. 0: read/write capture/compare registers at pca0cphn and pca0cpln. 1: read/write auto-reload registers at pca0cphn and pca0cpln. 6ecov cycle overflow interrupt enable. this bit sets the masking of the cycl e overflow flag (covf) interrupt. 0: covf will not generate pca interrupts. 1: a pca interrupt will be gene rated when covf is set. 5covf cycle overflow flag. this bit indicates an overflow of the 8th, 9th, 10th, or 11th bit of the main pca counter (pca0). the specif ic bit used for this flag depends on the setting of the cycle length se lect bits. the bit can be set by hardware or software, but must be cleared by software. 0: no overflow has occurred since the last time this bit was cleared. 1: an overflow has occurred since t he last time this bit was cleared. 4:2 unused unused. read = 000b; write = don?t care. 1:0 clsel[1:0] cycle length select. when 16-bit pwm mode is not selected, these bits select the length of the pwm cycle, between 8, 9, 10, or 11 bits. this affects all channels configured for pwm which are not us ing 16-bit pwm mode. these bits are ignored for individual channels configured to16-bit pwm mode. 00: 8 bits. 01: 9 bits. 10: 10 bits. 11: 11 bits. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 291 c8051f39x/37x sfr address = 0xce; sfr page = all pages sfr definition 32.4. pca0clr: pc a comparator clear control bit76543210 name cpcpol cpce2 cpce1 cpce0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7cpcpol comparator clear polarity. selects the polarity of the comparator result that will clear the pca channel(s). 0: pca channel(s) will be cleared when comparator re sult goes logic high 1: pca channel(s) will be cleared when comparator re sult goes logic low 6:3 reserved must write 0000b. 2 cpce2 comparator clear enable for cex2. enables the comparator clear function on pca channel 2. 1 cpce1 comparator clear enable for cex1. enables the comparator clear function on pca channel 1. 0 cpce0 comparator clear enable for cex0. enables the comparator clear function on pca channel 0. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 292 preliminary rev. 0.71 sfr addresses: pca0cpm0 = 0xda , pca0cpm1 = 0xdb , pca0cpm2 = 0xdc sfr pages: pca0cpm0 = all pages, pca0 cpm1 = all pages, pca0cpm2 = all pages sfr definition 32.5. pca0cpmn: pca capture/compare mode bit76543210 name pwm16n ecomn cappn capnn matn togn pwmn eccfn type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7pwm16n 16-bit pulse width modulation enable. this bit enables 16-bit mode when pulse width modulation mode is enabled. 0: 8 to 11-bit pwm selected. 1: 16-bit pwm selected. 6ecomn comparator function enable. this bit enables the comparator function for pca module n when set to 1. 5 cappn capture positive function enable. this bit enables the positive edge captur e for pca module n when set to 1. 4capnn capture negative function enable. this bit enables the negative edge captur e for pca module n when set to 1. 3matn match function enable. this bit enables the match function for pca module n when set to 1. when enabled, matches of the pca counter with a module 's capture/compare register cause the ccfn bit in pca0md register to be set to logic 1. 2 togn toggle function enable. this bit enables the toggle function for pca module n when set to 1. when enabled, matches of the pca counter with a module 's capture/compare register cause the logic level on the cexn pin to toggle. if the pwmn bit is also set to logic 1, the mod- ule operates in frequency output mode. 1pwmn pulse width modulation mode enable. this bit enables the pwm function for pca module n when set to 1. when enabled, a pulse width modulated signal is output on the cexn pin. 8 to 11-bit pwm is used if pwm16n is cleared; 16-bit mode is used if pwm16n is set to logic 1. if the togn bit is also set, the module operates in frequency output mode. 0eccfn capture/compare flag interrupt enable. this bit sets the masking of the capture/compare flag (ccfn) interrupt. 0: disable ccfn interrupts. 1: enable a capture/compare flag interrupt request when ccfn is set. note: when the wdte bit is set to 1, the pca0cpm2 register cannot be modified, and module 2 acts as the watchdog timer. to change the contents of the pca0cpm2 register or the function of module 2, the watchdog timer must be disabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 293 c8051f39x/37x sfr address = 0xf9; sfr page = all pages sfr address = 0xfa; sfr page = all pages sfr definition 32.6. pca0l: pca counter/timer low byte bit76543210 name pca0[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0[7:0] pca counter/timer low byte. the pca0l register holds the low byte (lsb) of the 16-bit pca counter/ timer. note: when the wdte bit is set to 1, the pca0l register canno t be modified by software. to change the contents of the pca0l register, the watchdog timer must first be disabled. sfr definition 32.7. pca0h: pca counter/timer high byte bit76543210 name pca0[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0[15:8] pca counter/timer high byte. the pca0h register holds the high byte (msb) of the 16-bit pca counter/timer. reads of this regi ster will read the contents of a ?snapshot? register, whose contents are updated only when the con- tents of pca0l are read (see section 32.1). note: when the wdte bit is set to 1, the pca0h register cannot be modified by software. to change the contents of the pca0h register, the watchdog timer must first be disabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 294 preliminary rev. 0.71 sfr addresses: pca0cpl0 = 0xfb , pca0cpl1 = 0xe9 , pca0cpl2 = 0xeb sfr pages: pca0cpl0 = all pages, pca0 cpl1 = all pages, pca0cpl2 = all pages sfr addresses: pca0cph0 = 0xfc , pca0cph1 = 0xea , pca0cph2 = 0xec sfr pages: pca0cph0 = all pages, pca0 cph1 = all pages, pca0cph2 = all pages sfr definition 32.8. pca0cpln: pca capture module low byte bit76543210 name pca0cpn[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0cpn[7:0] pca capture module low byte. the pca0cpln register holds the low byte (lsb) of the 16-bit capture module n. this register address also allows access to the low byte of the corresponding pca channel?s auto-reload value for 9, 10, or 11- bit pwm mode. the arsel bit in register pca0pwm controls which register is accessed. note: a write to this register will clear the module?s ecomn bit to a 0. sfr definition 32.9. pca0cphn: pca capture module high byte bit76543210 name pca0cpn[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0cpn[15:8] pca capture module high byte. the pca0cphn register holds the high byte (msb) of the 16-bit cap- ture module n. this register address also allows access to the high byte of the corre- sponding pca channel?s auto-reload value for 9, 10, or 11-bit pwm mode. the arsel bit in register pc a0pwm controls which register is accessed. note: a write to this register will set the module?s ecomn bit to a 1. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 295 c8051f39x/37x 33. c2 interface c8051f39x/37x devices include an on -chip silicon labs 2-wire (c2) d ebug interface to allow flash pro- gramming and in-system debugging with the production pa rt installed in the end a pplication. the c2 inter- face uses a clock signal (c2ck) and a bi-directiona l c2 data signal (c2d) to transfer information between the device and a host system. see the c2 interfac e specification for details on the c2 protocol. 33.1. c2 interface registers the following describes the c2 registers necessary to perform flash programming through the c2 inter- face. all c2 registers are accessed through the c2 inte rface as described in the c2 interface specification. c2 register definition 33.1. c2add: c2 address bit76543210 name c2add[7:0] type r/w reset 00000000 bit name function 7:0 c2add[7:0] c2 address. the c2add register is accessed via the c2 interface to select the target data register for c2 data read and data write commands. address description 0x00 selects the device id register for data read instructions 0x01 selects the revision id register for data read instructions 0x02 selects the c2 flash programming control register for data read/write instructions 0xb4 selects the c2 flash programm ing data register for data read/ write instructions www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 296 preliminary rev. 0.71 c2 address: 0x00 c2 address: 0x01 c2 register definition 33. 2. deviceid: c2 device id bit76543210 name deviceid[7:0] type r/w reset 00101011 bit name function 7:0 deviceid[7:0] device id. this read-only register returns the 8- bit device id: 0x2b (c8051f39x/37x). c2 register definition 33. 3. revid: c2 revision id bit76543210 name revid[7:0] type r/w reset varies varies varies varies varies varies varies varies bit name function 7:0 revid[7:0] revision id. this read-only register returns the 8-bit revision id. for example: 0x00 = revision a. www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 297 c8051f39x/37x c2 address: 0x02 c2 address: 0xb4 c2 register definition 33.4. fpct l: c2 flash programming control bit76543210 name fpctl[7:0] type r/w reset 00000000 bit name function 7:0 fpctl[7:0] flash programming control register. this register is used to enable flash pr ogramming via the c2 interface. to enable c2 flash programming, the following codes mu st be written in order: 0x02, 0x01. note that once c2 flash programming is enabled, a system reset must be issued to resume normal operation. c2 register definition 33.5. fp dat: c2 flash programming data bit76543210 name fpdat[7:0] type r/w reset 00000000 bit name function 7:0 fpdat[7:0] c2 flash programming data register. this register is used to pass flash commands, addresses, and data during c2 flash accesses. valid commands are listed below. code command 0x06 flash block read 0x07 flash block write 0x08 flash page erase 0x03 device erase www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 298 preliminary rev. 0.71 33.2. c2 pin sharing the c2 protocol allows the c2 pins to be shared wi th user functions so that in-system debugging and flash programming may be performed. this is possible because c2 communication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. in this halted state, the c2 interface c an safely ?borrow? the c2ck (rst ) and c2d pins. in most applications, external resistors are required to isolate c2 interface traffic from the user application. a typical isolation configuration is shown in figure 33.1. figure 33.1. typical c2 pin sharing the configuration in figure 33.1 assumes the following: 1. the user input (b) cannot change stat e while the target device is halted. 2. the rst pin on the target device is used as an input only. additional resistors may be necessary depending on the specific application. c2d c2ck /reset (a) input (b) output (c) c2 interface master c8051fxxx www.datasheet.net/ datasheet pdf - http://www..co.kr/ preliminary rev. 0.71 299 d ocument c hange l ist revision 0.1 to revision 0.7 ? added section 8.1 ?temperature in two?s complement? ? changed clock cycles for ?cjne a, direct, re? to ?4/ 6? in section 15. ?cip-15 microcontroller? ? changed bit 5 of crc0cnt to reserved in section 23. ?cyclic redundancy check unit? (crc0) ? changed sfrpgcn reset value to ?0x01? in section 19. ?special function registers? ? added section 19.2 ?interrupts and automatic sfr paging? ? added section 19.3 ?sfr page stack example? ? corrected incorrect references to c8501f34x in section 2. ?ordering information? ? removed ?the c8051f37x does not include the 4x clock multiplier? bullet point from section 3.1 ? removed ?external osc illator c and rc modes? bullet point from section 3.1 ? updated the block diagram on the front page to show eeprom and 500 ksps adc ? removed references to the reg0md bit and low power mode in section 13.1 ? removed reg0md bit in the reg0cn sfr definition. this bit (bit 2) is now reserved. ? section 22. ?eeprom? co mpletely rewritten ? moved the ?from iph, eiph1 or eiph2? text from the lsb column to the msb column in table 20.1 ? moved the ?from ip, eip1 or eip2? text from the msb column to the lsb column in table 20.1 ? changed figure 27.4 to show all five footnotes ? changed figure 27.5 to show correct sf signals and all five footnotes ? added 5 v tolerance and lock byte address bullet points to section 3.1. ?hardware incompatibilities? revision 0.7 to revision 0.71 ? updated part numbers in table 2.1 on page 20. ? updated replacement part numbers in table 3.1 on page 21 to match flash sizes. ? corrected units for normal and active mode idd (v dd = 3.0 v, f = 80 khz) in table 7.2 on page 33. ? updated maximum normal m ode idd in table 7.2 on page 33. ? added eesda and eescl dc electrical characteristics to table 7.3 on page 34. ? added eeprom supply current to table 7.6 on page 36. ? added maximum eescl clock frequency to table 7.6 on page 36. ? updated typical inl and dnl in table 7.10 on page 38. ? updated resolution in table 7.12 on page 39. ? updated typical and maximum inl and dnl in table 7.15 on page 41. ? updated typical full scale error in table 7.15 on page 41. ? updated references to table 28.3 in the smb0cn and smb1cn sfr definitions. www.datasheet.net/ datasheet pdf - http://www..co.kr/ c8051f39x/37x 300 preliminary rev. 0.71 c ontact i nformation silicon laboratories inc. silicon laboratories inc. 400 west cesar chavez austin, tx 78701 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders the information in this document is believed to be accurate in al l respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no re sponsibility for errors and omissions, and disclaims responsibi lity for any consequen ces resulting from the use of information included herein. additi onally, silicon laborator ies assumes no responsibility for the fun ction- ing of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice. sili con laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does silicon laboratories assume any liabi lity arising out of the application or use of any product or circuit, and specifi cally disclaims any and all liability, including without limitation consequential or incident al damages. silicon laboratories product s are not designed, intended, or authorized for use in applications in tended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a si tuation where personal injury or death may occur. should buyer purchase or use silicon laboratories prod ucts for any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. www.datasheet.net/ datasheet pdf - http://www..co.kr/ |
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